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| author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2012-05-04 22:18:21 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-08 14:15:51 +0200 |
| commit | ecb978515c88183b111b8994acd6b572b1361a72 (patch) | |
| tree | e822de5e92160d578f8bb58df830f77a7730218f /drivers/gpu/drm/i915/intel_hdmi.c | |
| parent | drm/i915: break intel_infoframe_flags into _enable and _frequency (diff) | |
| download | linux-ecb978515c88183b111b8994acd6b572b1361a72.tar.xz linux-ecb978515c88183b111b8994acd6b572b1361a72.zip | |
drm/i915: disable the infoframe before changing it
That's what the VIDEO_DIP_CTL documentation says we need to do. Except
when it's the AVI InfoFrame and we're ironlake_write_infoframe.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 661fed48c5b9..6c96bb54e967 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -153,6 +153,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + val &= ~intel_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(VIDEO_DIP_CTL, val); @@ -185,6 +186,13 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + /* The DIP control register spec says that we need to update the AVI + * infoframe without clearing its enable bit */ + if (frame->type == DIP_TYPE_AVI) + val |= VIDEO_DIP_ENABLE_AVI; + else + val &= ~intel_infoframe_enable(frame); + val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); @@ -217,6 +225,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); + val &= ~intel_infoframe_enable(frame); val |= VIDEO_DIP_ENABLE; I915_WRITE(reg, val); |