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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-07 23:34:16 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-15 01:20:28 +0200 |
| commit | 2fa2fe9a142cf8c8a30916ccf7ca6a27019fd6d2 (patch) | |
| tree | 97a8db0f03d4a4a28523afb4c0d0b8544e318f1e /drivers/gpu/drm/i915/intel_lvds.c | |
| parent | drm/i915: implement WADPOClockGatingDisable for LPT (diff) | |
| download | linux-2fa2fe9a142cf8c8a30916ccf7ca6a27019fd6d2.tar.xz linux-2fa2fe9a142cf8c8a30916ccf7ca6a27019fd6d2.zip | |
drm/i915: panel fitter hw state readout&check support
Pfit state readout is a bit ugly on gen2/3 due to the intermingling
with the lvds state, but alas.
Also note that since state is always cleared to zero we can
unconditonally compare all the state and completely neglect the actual
platform we're running on.
v2: Properly check for the pfit power domain on haswell.
v3: Don't check pgm_ratios on gen4+, they're auto-computed by the hw.
v4: Properly clear the lvds border bits, upset the state checker a
bit.
v5: Unconditionally read out panel dither settings on gen2/3.
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lvds.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lvds.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e34e290c29eb..36fe291172ee 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -116,6 +116,7 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) } /* set the corresponsding LVDS_BORDER bit */ + temp &= ~LVDS_BORDER_ENABLE; temp |= intel_crtc->config.gmch_pfit.lvds_border_bits; /* Set the B0-B3 data pairs corresponding to whether we're going to * set the DPLLs for dual-channel mode or not. |