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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-01-19 12:50:50 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-01-27 09:50:46 +0100
commitaf5a75a37501b30a8230ee9493d9184e896a2faa (patch)
tree23534035d2a4e87b6a1421374e16f916e4921a47 /drivers/gpu/drm/i915/intel_pm.c
parentdrm/i915: Configure GEN6_RP_DOWN_TIMEOUT on CHV (diff)
downloadlinux-af5a75a37501b30a8230ee9493d9184e896a2faa.tar.xz
linux-af5a75a37501b30a8230ee9493d9184e896a2faa.zip
Revert "Revert "drm/i915/chv: Use timeout mode for RC6 on chv""
The performance regression from the CHV RC6 EI->TO change is now fixed so re-enable TO mode for better RC6 resicency. This reverts commit e85a5c7989c5be8fe30acc35eba9fb54b3450f36. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8c7a07d3930f..8ee65da932d7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4724,7 +4724,8 @@ static void cherryview_enable_rps(struct drm_device *dev)
I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
I915_WRITE(GEN6_RC_SLEEP, 0);
- I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+ /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */
+ I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
/* allows RC6 residency counter to work */
I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4738,7 +4739,7 @@ static void cherryview_enable_rps(struct drm_device *dev)
/* 3: Enable RC6 */
if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
(pcbr >> VLV_PCBR_ADDR_SHIFT))
- rc6_mode = GEN6_RC_CTL_EI_MODE(1);
+ rc6_mode = GEN7_RC_CTL_TO_MODE;
I915_WRITE(GEN6_RC_CONTROL, rc6_mode);