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| author | Matt Roper <matthew.d.roper@intel.com> | 2019-12-24 02:20:26 +0100 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2019-12-27 19:46:39 +0100 |
| commit | 4ca153827f65a6779392fff668c46f9cc54d414b (patch) | |
| tree | 12caa4d3bfd9bddfba3111ee67018618d939b6db /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl (diff) | |
| download | linux-4ca153827f65a6779392fff668c46f9cc54d414b.tar.xz linux-4ca153827f65a6779392fff668c46f9cc54d414b.zip | |
drm/i915/tgl: Extend Wa_1408615072 to tgl
Although the workaround number and description are the same, the vsunit
clock gate disable bit has moved to a new register and location on
gen12.
Bspec: 52890
Bspec: 52758
Cc: stable@kernel.vger.org
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191224012026.3157766-4-matthew.d.roper@intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index cbd83ece7306..58db5a7d27ec 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6605,6 +6605,10 @@ static void tgl_init_clock_gating(struct drm_i915_private *dev_priv) u32 vd_pg_enable = 0; unsigned int i; + /* Wa_1408615072:tgl */ + intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2, + 0, VSUNIT_CLKGATE_DIS_TGL); + /* This is not a WA. Enable VD HCP & MFX_ENC powergate */ for (i = 0; i < I915_MAX_VCS; i++) { if (HAS_ENGINE(dev_priv, _VCS(i))) |