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authorVille Syrjälä <ville.syrjala@linux.intel.com>2013-11-28 16:29:57 +0100
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-12 15:58:09 +0100
commit159f98750e413f5d6e63d1131417c5310ea175fb (patch)
treedc518390d3aecfe930792430837fb2cda02011b7 /drivers/gpu/drm/i915/intel_pm.c
parentdrm/i915: Gen2 FBC1 CFB pitch wants 32B units (diff)
downloadlinux-159f98750e413f5d6e63d1131417c5310ea175fb.tar.xz
linux-159f98750e413f5d6e63d1131417c5310ea175fb.zip
drm/i915: FBC_CONTROL2 is gen4 only
Gen2 and gen3 don't have the FBC_CONTROL2 register, so don't touch it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 599d445f7ce9..d7cb6bf5712d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -98,7 +98,7 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int cfb_pitch;
int plane, i;
- u32 fbc_ctl, fbc_ctl2;
+ u32 fbc_ctl;
cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
if (fb->pitches[0] < cfb_pitch)
@@ -115,11 +115,15 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
I915_WRITE(FBC_TAG + (i * 4), 0);
- /* Set it up... */
- fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
- fbc_ctl2 |= plane;
- I915_WRITE(FBC_CONTROL2, fbc_ctl2);
- I915_WRITE(FBC_FENCE_OFF, crtc->y);
+ if (IS_GEN4(dev)) {
+ u32 fbc_ctl2;
+
+ /* Set it up... */
+ fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
+ fbc_ctl2 |= plane;
+ I915_WRITE(FBC_CONTROL2, fbc_ctl2);
+ I915_WRITE(FBC_FENCE_OFF, crtc->y);
+ }
/* enable it... */
fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;