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authorDave Airlie <airlied@redhat.com>2013-12-12 01:38:43 +0100
committerDave Airlie <airlied@redhat.com>2013-12-12 01:38:43 +0100
commit25945b66903dade5e1297742b4ed0746a77eb5c5 (patch)
treee6157162ea4ef009d25a73acd2ec6694e349737e /drivers/gpu/drm/i915/intel_pm.c
parentMerge branch 'bdw-fixes' of git://people.freedesktop.org/~danvet/drm-intel in... (diff)
parentdrm/i915: don't update the dri1 breadcrumb with modesetting (diff)
downloadlinux-25945b66903dade5e1297742b4ed0746a77eb5c5.tar.xz
linux-25945b66903dade5e1297742b4ed0746a77eb5c5.zip
Merge tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Just a bunch of regression fixes plus a few patches for long-standing issues in gem corner-cases that we've hunted down in the past weeks. Since apparently people hit those in the wild (and we also have nice igts for them) I've opted for -fixes and cc: stable. There's 1-2 things oustanding on top of this where I'm still waiting on confirmation from testing, but nothing really scary. * tag 'drm-intel-fixes-2013-12-11' of git://people.freedesktop.org/~danvet/drm-intel: drm/i915: don't update the dri1 breadcrumb with modesetting drm/i915: Repeat eviction search after idling the GPU drm/i915: Fix use-after-free in do_switch drm/i915: fix pm init ordering drm/i915: Hold mutex across i915_gem_release drm/i915: Skip clock checks on BDW drm/i915: Do not clobber config status after a forced restore of hw state drm/i915: Take modeset locks around intel_modeset_setup_hw_state()
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa5f99c906ef..3657ab43c8fd 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6146,10 +6146,19 @@ int vlv_freq_opcode(int ddr_freq, int val)
return val;
}
-void intel_pm_init(struct drm_device *dev)
+void intel_pm_setup(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ mutex_init(&dev_priv->rps.hw_lock);
+
+ mutex_init(&dev_priv->pc8.lock);
+ dev_priv->pc8.requirements_met = false;
+ dev_priv->pc8.gpu_idle = false;
+ dev_priv->pc8.irqs_disabled = false;
+ dev_priv->pc8.enabled = false;
+ dev_priv->pc8.disable_count = 2; /* requirements_met + gpu_idle */
+ INIT_DELAYED_WORK(&dev_priv->pc8.enable_work, hsw_enable_pc8_work);
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
intel_gen6_powersave_work);
}