diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-14 10:18:09 +0100 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-02-16 14:05:36 +0100 |
| commit | a19c1d00b0d350fb7b75c6c4da91887f66114a7d (patch) | |
| tree | 3a2ee5d2e52d885ccaac44b1da5ffc1340f1c9ae /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Widen the QGV point mask (diff) | |
| download | linux-a19c1d00b0d350fb7b75c6c4da91887f66114a7d.tar.xz linux-a19c1d00b0d350fb7b75c6c4da91887f66114a7d.zip | |
drm/i915: Unconfuse pre-icl vs. icl+ intel_sagv_{pre,post}_plane_update()
intel_sagv_{pre,post}_plane_update() can accidentally forget
to bail out early on pre-icl and proceed down the icl+ codepath
at the end of the function. Fortunately it'll bail out before
it gets too far due to old_qgv_mask==new_qgv_mask==0 so no real
bug here. But lets make the code less confusing anyway.
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220214091811.13725-5-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 191bb3966505..9f5e3c399f8d 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3802,8 +3802,9 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (DISPLAY_VER(dev_priv) < 11 && !intel_can_enable_sagv(dev_priv, new_bw_state)) { - intel_disable_sagv(dev_priv); + if (DISPLAY_VER(dev_priv) < 11) { + if (!intel_can_enable_sagv(dev_priv, new_bw_state)) + intel_disable_sagv(dev_priv); return; } @@ -3853,8 +3854,9 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state) if (!new_bw_state) return; - if (DISPLAY_VER(dev_priv) < 11 && intel_can_enable_sagv(dev_priv, new_bw_state)) { - intel_enable_sagv(dev_priv); + if (DISPLAY_VER(dev_priv) < 11) { + if (intel_can_enable_sagv(dev_priv, new_bw_state)) + intel_enable_sagv(dev_priv); return; } |