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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-01-21 18:37:58 +0100 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-01-27 09:51:09 +0100 |
| commit | 14bc16e3987863add16bae01e83eb8050af83ea6 (patch) | |
| tree | cbd9152a9fbd68779e70c81d7dd79ecdcd9c9e81 /drivers/gpu/drm/i915 | |
| parent | drm/i915: Simplify flush_cpu_write_domain (diff) | |
| download | linux-14bc16e3987863add16bae01e83eb8050af83ea6.tar.xz linux-14bc16e3987863add16bae01e83eb8050af83ea6.zip | |
drm/i915: Implement Wa4x4STCOptimizationDisable:chv
Wa4x4STCOptimizationDisable got only implemented for BDW, but according
to the w/a database CHV needs it too, so add it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d7aa5c464d96..2a1a178153e1 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -851,6 +851,10 @@ static int chv_init_workarounds(struct intel_engine_cs *ring) */ WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); + /* Wa4x4STCOptimizationDisable:chv */ + WA_SET_BIT_MASKED(CACHE_MODE_1, + GEN8_4x4_STC_OPTIMIZATION_DISABLE); + /* Improve HiZ throughput on CHV. */ WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); |