diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-06-20 13:10:37 +0200 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-08-07 23:30:49 +0200 |
| commit | 02a726fc6b2892a5fe4704060594b1af9c2ff953 (patch) | |
| tree | f2800f87697232d4a0d8c781f847dccc28f9aa31 /drivers/gpu/drm/msm/adreno | |
| parent | drm/msm/a6xx: Add some missing header definitions (diff) | |
| download | linux-02a726fc6b2892a5fe4704060594b1af9c2ff953.tar.xz linux-02a726fc6b2892a5fe4704060594b1af9c2ff953.zip | |
drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL
We have the necessary information, so explain which bit does what.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543332/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 9be3260c8033..e0c90393cda5 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -930,7 +930,10 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) * protect violation and select the last span to protect from the start * address all the way to the end of the register address space */ - gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3)); + gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, + A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN | + A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN | + A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE); for (i = 0; i < count - 1; i++) gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]); |