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authorRob Clark <robdclark@chromium.org>2022-03-04 01:52:14 +0100
committerRob Clark <robdclark@chromium.org>2022-03-04 20:50:41 +0100
commit57cfe41c5f50aaad92942ff9947c6cee54b9d314 (patch)
tree87a253986b304222cec9ae2138294dab9bcc48e7 /drivers/gpu/drm/msm/adreno
parentdt-bindings: display/msm: add missing brace in dpu-qcm2290.yaml (diff)
downloadlinux-57cfe41c5f50aaad92942ff9947c6cee54b9d314.tar.xz
linux-57cfe41c5f50aaad92942ff9947c6cee54b9d314.zip
drm/msm: Update generated headers
Update headers from mesa commit: commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Author: Rob Clark <robclark@freedesktop.org> AuthorDate: Wed Mar 2 17:11:10 2022 -0800 freedreno/registers: Add a couple regs we need for kernel Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221> Signed-off-by: Rob Clark <robdclark@chromium.org> [for display bits:] Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20220304005317.776110-2-robdclark@gmail.com
Diffstat (limited to 'drivers/gpu/drm/msm/adreno')
-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h26
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h30
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx.xml.h112
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx.xml.h63
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx.xml.h674
-rw-r--r--drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h26
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h31
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h46
8 files changed, 638 insertions, 370 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 4ff529576093..afa6023346c4 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index e106b65abe26..520ae3f375a1 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
@@ -1466,7 +1466,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endi
#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
-#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
+#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
#define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
@@ -1476,7 +1476,7 @@ static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
}
#define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
-#define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
+#define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
#define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
index b26ede96ae2a..7e5c21015d10 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
-
-Copyright (C) 2013-2021 by the following authors:
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
+
+Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -837,6 +837,7 @@ enum a4xx_tex_type {
A4XX_TEX_2D = 1,
A4XX_TEX_CUBE = 2,
A4XX_TEX_3D = 3,
+ A4XX_TEX_BUFFER = 4,
};
#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
@@ -1360,7 +1361,7 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
-#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
+#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
@@ -1371,7 +1372,7 @@ static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
-#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
+#define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
@@ -2541,6 +2542,8 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
}
#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
+#define A4XX_SP_FS_MRT_REG_COLOR_SINT 0x00000400
+#define A4XX_SP_FS_MRT_REG_COLOR_UINT 0x00000800
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
@@ -2550,6 +2553,40 @@ static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
+#define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
+#define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
+static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
+{
+ return ((val) << A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
+}
+#define A4XX_SP_CS_CTRL_REG0_VARYING 0x00000002
+#define A4XX_SP_CS_CTRL_REG0_CACHEINVALID 0x00000004
+#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
+#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
+static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
+{
+ return ((val) << A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
+}
+#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
+#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
+static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
+{
+ return ((val) << A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
+}
+#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
+#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
+static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
+{
+ return ((val) << A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK;
+}
+#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
+#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
+static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
+{
+ return ((val) << A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
+}
+#define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE 0x00200000
+#define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00400000
#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
@@ -3795,12 +3832,18 @@ static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
-#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x000000ff
+#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x00000fff
#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
{
return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
}
+#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK 0x00fff000
+#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT 12
+static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK;
+}
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
@@ -3809,8 +3852,32 @@ static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
}
#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
+#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK 0x00000fff
+#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT 0
+static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK;
+}
+#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK 0x00fff000
+#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT 12
+static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK;
+}
#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
+#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK 0x00000fff
+#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT 0
+static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK;
+}
+#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK 0x00fff000
+#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT 12
+static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK;
+}
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
@@ -3819,6 +3886,12 @@ static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
+#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK 0x00000fff
+#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT 0
+static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val)
+{
+ return ((val) << A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK;
+}
#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
@@ -4130,7 +4203,7 @@ static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
{
return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
}
-#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
+#define A4XX_TEX_CONST_0_TYPE__MASK 0xe0000000
#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
{
@@ -4158,6 +4231,7 @@ static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
{
return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
}
+#define A4XX_TEX_CONST_2_BUFFER 0x00000040
#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
index 1e575ca1f270..2505b4e43ca0 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
-
-Copyright (C) 2013-2021 by the following authors:
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
+
+Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -872,6 +872,7 @@ enum a5xx_tex_type {
A5XX_TEX_2D = 1,
A5XX_TEX_CUBE = 2,
A5XX_TEX_3D = 3,
+ A5XX_TEX_BUFFER = 4,
};
#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
@@ -2830,7 +2831,9 @@ static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
-#define A5XX_GRAS_CNTL_SIZE 0x00000008
+#define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
+#define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
+#define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
@@ -2911,7 +2914,12 @@ static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
}
#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
-#define A5XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
+#define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
+#define A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
+static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
+{
+ return ((val) << A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A5XX_GRAS_SU_CNTL_LINE_MODE__MASK;
+}
#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
@@ -3166,7 +3174,9 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
-#define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
+#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
+#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
+#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
@@ -3490,7 +3500,7 @@ static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
-#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
+#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
@@ -3498,7 +3508,7 @@ static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
{
return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
}
-#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
+#define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
@@ -5034,6 +5044,7 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
}
#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
+#define A5XX_RB_2D_SRC_INFO_SRGB 0x00002000
#define REG_A5XX_RB_2D_SRC_LO 0x00002108
@@ -5073,6 +5084,7 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
}
#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
+#define A5XX_RB_2D_DST_INFO_SRGB 0x00002000
#define REG_A5XX_RB_2D_DST_LO 0x00002111
@@ -5138,6 +5150,7 @@ static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val
return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
}
#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
+#define A5XX_GRAS_2D_SRC_INFO_SRGB 0x00002000
#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
@@ -5159,10 +5172,7 @@ static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
}
#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
-
-#define REG_A5XX_UNKNOWN_2100 0x00002100
-
-#define REG_A5XX_UNKNOWN_2180 0x00002180
+#define A5XX_GRAS_2D_DST_INFO_SRGB 0x00002000
#define REG_A5XX_UNKNOWN_2184 0x00002184
@@ -5316,7 +5326,7 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
}
#define REG_A5XX_TEX_CONST_2 0x00000002
-#define A5XX_TEX_CONST_2_UNK4 0x00000010
+#define A5XX_TEX_CONST_2_BUFFER 0x00000010
#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
@@ -5329,13 +5339,12 @@ static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
{
return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
}
-#define A5XX_TEX_CONST_2_TYPE__MASK 0x60000000
+#define A5XX_TEX_CONST_2_TYPE__MASK 0xe0000000
#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
{
return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
}
-#define A5XX_TEX_CONST_2_UNK31 0x80000000
#define REG_A5XX_TEX_CONST_3 0x00000003
#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index a3cb3d988ba4..b03e2c413ab1 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
-
-Copyright (C) 2013-2021 by the following authors:
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
+
+Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -132,9 +132,21 @@ enum a6xx_format {
FMT6_G8R8B8R8_422_UNORM = 140,
FMT6_R8G8R8B8_422_UNORM = 141,
FMT6_R8_G8B8_2PLANE_420_UNORM = 142,
+ FMT6_NV21 = 143,
FMT6_R8_G8_B8_3PLANE_420_UNORM = 144,
FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145,
- FMT6_8_PLANE_UNORM = 148,
+ FMT6_NV12_Y = 148,
+ FMT6_NV12_UV = 149,
+ FMT6_NV12_VU = 150,
+ FMT6_NV12_4R = 151,
+ FMT6_NV12_4R_Y = 152,
+ FMT6_NV12_4R_UV = 153,
+ FMT6_P010 = 154,
+ FMT6_P010_Y = 155,
+ FMT6_P010_UV = 156,
+ FMT6_TP10 = 157,
+ FMT6_TP10_Y = 158,
+ FMT6_TP10_UV = 159,
FMT6_Z24_UNORM_S8_UINT = 160,
FMT6_ETC2_RG11_UNORM = 171,
FMT6_ETC2_RG11_SNORM = 172,
@@ -885,6 +897,44 @@ enum a6xx_ztest_mode {
A6XX_EARLY_LRZ_LATE_Z = 2,
};
+enum a6xx_sequenced_thread_dist {
+ DIST_SCREEN_COORD = 0,
+ DIST_ALL_TO_RB0 = 1,
+};
+
+enum a6xx_single_prim_mode {
+ NO_FLUSH = 0,
+ FLUSH_PER_OVERLAP_AND_OVERWRITE = 1,
+ FLUSH_PER_OVERLAP = 3,
+};
+
+enum a6xx_raster_mode {
+ TYPE_TILED = 0,
+ TYPE_WRITER = 1,
+};
+
+enum a6xx_raster_direction {
+ LR_TB = 0,
+ RL_TB = 1,
+ LR_BT = 2,
+ RB_BT = 3,
+};
+
+enum a6xx_render_mode {
+ RENDERING_PASS = 0,
+ BINNING_PASS = 1,
+};
+
+enum a6xx_buffers_location {
+ BUFFERS_IN_GMEM = 0,
+ BUFFERS_IN_SYSMEM = 3,
+};
+
+enum a6xx_fragcoord_sample_mode {
+ FRAGCOORD_CENTER = 0,
+ FRAGCOORD_SAMPLE = 3,
+};
+
enum a6xx_rotation {
ROTATE_0 = 0,
ROTATE_90 = 1,
@@ -912,6 +962,10 @@ enum a6xx_threadsize {
THREAD128 = 1,
};
+enum a6xx_isam_mode {
+ ISAMMODE_GL = 2,
+};
+
enum a6xx_tex_filter {
A6XX_TEX_NEAREST = 0,
A6XX_TEX_LINEAR = 1,
@@ -955,6 +1009,7 @@ enum a6xx_tex_type {
A6XX_TEX_2D = 1,
A6XX_TEX_CUBE = 2,
A6XX_TEX_3D = 3,
+ A6XX_TEX_BUFFER = 4,
};
#define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
@@ -1292,6 +1347,10 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
#define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b
+#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e
+
+#define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f
+
#define REG_A6XX_RBBM_ISDB_CNT 0x00000533
#define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540
@@ -1934,6 +1993,8 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
+#define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00
+
#define REG_A6XX_VSC_BIN_SIZE 0x00000c02
#define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
@@ -2076,9 +2137,9 @@ static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val)
#define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
#define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
#define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
-#define A6XX_GRAS_CNTL_SIZE 0x00000008
-#define A6XX_GRAS_CNTL_UNK4 0x00000010
-#define A6XX_GRAS_CNTL_SIZE_PERSAMP 0x00000020
+#define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
+#define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
+#define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
#define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
#define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6
static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val)
@@ -2185,7 +2246,12 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val)
{
return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK;
}
-#define A6XX_GRAS_SU_CNTL_MSAA_ENABLE 0x00002000
+#define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
+#define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
+static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
+{
+ return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK;
+}
#define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000
#define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15
static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val)
@@ -2269,9 +2335,25 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK;
}
-#define REG_A6XX_GRAS_UNKNOWN_8099 0x00008099
+#define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1
+static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val)
+{
+ return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK;
+}
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030
+#define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4
+static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val)
+{
+ return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK;
+}
-#define REG_A6XX_GRAS_UNKNOWN_809A 0x0000809a
+#define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a
+#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001
+#define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002
#define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b
#define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001
@@ -2285,7 +2367,44 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val)
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001
#define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002
-#define REG_A6XX_GRAS_UNKNOWN_80A0 0x000080a0
+#define REG_A6XX_GRAS_SC_CNTL 0x000080a0
+#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007
+#define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0
+static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018
+#define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3
+static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020
+#define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5
+static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0
+#define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6
+static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100
+#define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8
+static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_UNK9__MASK 0x00000e00
+#define A6XX_GRAS_SC_CNTL_UNK9__SHIFT 9
+static inline uint32_t A6XX_GRAS_SC_CNTL_UNK9(uint32_t val)
+{
+ return ((val) << A6XX_GRAS_SC_CNTL_UNK9__SHIFT) & A6XX_GRAS_SC_CNTL_UNK9__MASK;
+}
+#define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000
#define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1
#define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f
@@ -2300,25 +2419,30 @@ static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK;
}
-#define A6XX_GRAS_BIN_CONTROL_BINNING_PASS 0x00040000
-#define A6XX_GRAS_BIN_CONTROL_UNK19__MASK 0x00080000
-#define A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT 19
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK19(uint32_t val)
+#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
+#define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
+{
+ return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK;
+}
+#define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
+#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
+#define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
{
- return ((val) << A6XX_GRAS_BIN_CONTROL_UNK19__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK19__MASK;
+ return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK;
}
-#define A6XX_GRAS_BIN_CONTROL_UNK20__MASK 0x00100000
-#define A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT 20
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK20(uint32_t val)
+#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
+#define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
{
- return ((val) << A6XX_GRAS_BIN_CONTROL_UNK20__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK20__MASK;
+ return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
}
-#define A6XX_GRAS_BIN_CONTROL_USE_VIZ 0x00200000
-#define A6XX_GRAS_BIN_CONTROL_UNK22__MASK 0x0fc00000
-#define A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT 22
-static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK22(uint32_t val)
+#define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000
+#define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27
+static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val)
{
- return ((val) << A6XX_GRAS_BIN_CONTROL_UNK22__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK22__MASK;
+ return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK;
}
#define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2
@@ -2558,14 +2682,21 @@ static inline uint32_t A6XX_GRAS_LRZ_CNTL_UNK6(uint32_t val)
return ((val) << A6XX_GRAS_LRZ_CNTL_UNK6__SHIFT) & A6XX_GRAS_LRZ_CNTL_UNK6__MASK;
}
-#define REG_A6XX_GRAS_UNKNOWN_8101 0x00008101
+#define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101
+#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001
+#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006
+#define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1
+static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
+{
+ return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK;
+}
-#define REG_A6XX_GRAS_2D_BLIT_INFO 0x00008102
-#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK 0x000000ff
-#define A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT 0
-static inline uint32_t A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT(enum a6xx_format val)
+#define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102
+#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff
+#define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0
+static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val)
{
- return ((val) << A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_INFO_COLOR_FORMAT__MASK;
+ return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK;
}
#define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103
@@ -2630,11 +2761,12 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK;
}
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK 0x00000078
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT 3
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK3(uint32_t val)
+#define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070
+#define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val)
{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK3__MASK;
+ return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK;
}
#define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
#define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
@@ -2663,11 +2795,11 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
{
return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK;
}
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK 0x20000000
-#define A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT 29
-static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK29(uint32_t val)
+#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
+#define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
+static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
{
- return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK29__MASK;
+ return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK;
}
#define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401
@@ -2740,7 +2872,9 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val)
return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK;
}
-#define REG_A6XX_GRAS_UNKNOWN_8600 0x00008600
+#define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600
+#define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080
+#define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800
#define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601
@@ -2763,43 +2897,55 @@ static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val)
{
return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK;
}
-#define A6XX_RB_BIN_CONTROL_BINNING_PASS 0x00040000
-#define A6XX_RB_BIN_CONTROL_UNK19__MASK 0x00080000
-#define A6XX_RB_BIN_CONTROL_UNK19__SHIFT 19
-static inline uint32_t A6XX_RB_BIN_CONTROL_UNK19(uint32_t val)
+#define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000
+#define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18
+static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val)
{
- return ((val) << A6XX_RB_BIN_CONTROL_UNK19__SHIFT) & A6XX_RB_BIN_CONTROL_UNK19__MASK;
+ return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK;
}
-#define A6XX_RB_BIN_CONTROL_UNK20__MASK 0x00100000
-#define A6XX_RB_BIN_CONTROL_UNK20__SHIFT 20
-static inline uint32_t A6XX_RB_BIN_CONTROL_UNK20(uint32_t val)
+#define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000
+#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000
+#define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22
+static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val)
{
- return ((val) << A6XX_RB_BIN_CONTROL_UNK20__SHIFT) & A6XX_RB_BIN_CONTROL_UNK20__MASK;
+ return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK;
}
-#define A6XX_RB_BIN_CONTROL_USE_VIZ 0x00200000
-#define A6XX_RB_BIN_CONTROL_UNK22__MASK 0x07c00000
-#define A6XX_RB_BIN_CONTROL_UNK22__SHIFT 22
-static inline uint32_t A6XX_RB_BIN_CONTROL_UNK22(uint32_t val)
+#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000
+#define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24
+static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val)
{
- return ((val) << A6XX_RB_BIN_CONTROL_UNK22__SHIFT) & A6XX_RB_BIN_CONTROL_UNK22__MASK;
+ return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK;
}
#define REG_A6XX_RB_RENDER_CNTL 0x00008801
-#define A6XX_RB_RENDER_CNTL_UNK3 0x00000008
-#define A6XX_RB_RENDER_CNTL_UNK4 0x00000010
-#define A6XX_RB_RENDER_CNTL_UNK5__MASK 0x00000060
-#define A6XX_RB_RENDER_CNTL_UNK5__SHIFT 5
-static inline uint32_t A6XX_RB_RENDER_CNTL_UNK5(uint32_t val)
+#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038
+#define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3
+static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val)
{
- return ((val) << A6XX_RB_RENDER_CNTL_UNK5__SHIFT) & A6XX_RB_RENDER_CNTL_UNK5__MASK;
+ return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK;
}
+#define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040
#define A6XX_RB_RENDER_CNTL_BINNING 0x00000080
-#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00001f00
+#define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700
#define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8
static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val)
{
return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK;
}
+#define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100
+#define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8
+static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
+{
+ return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK;
+}
+#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600
+#define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9
+static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val)
+{
+ return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK;
+}
+#define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800
+#define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000
#define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
#define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
@@ -2945,9 +3091,9 @@ static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val)
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
#define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
-#define A6XX_RB_RENDER_CONTROL0_SIZE 0x00000008
-#define A6XX_RB_RENDER_CONTROL0_UNK4 0x00000010
-#define A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP 0x00000020
+#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
+#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
+#define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
#define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
@@ -2961,11 +3107,15 @@ static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
#define A6XX_RB_RENDER_CONTROL1_UNK1 0x00000002
#define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004
#define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008
-#define A6XX_RB_RENDER_CONTROL1_UNK4 0x00000010
-#define A6XX_RB_RENDER_CONTROL1_UNK5 0x00000020
+#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030
+#define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4
+static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val)
+{
+ return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK;
+}
#define A6XX_RB_RENDER_CONTROL1_SIZE 0x00000040
-#define A6XX_RB_RENDER_CONTROL1_UNK7 0x00000080
-#define A6XX_RB_RENDER_CONTROL1_UNK8 0x00000100
+#define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080
+#define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100
#define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b
#define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001
@@ -3299,7 +3449,7 @@ static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val)
}
#define REG_A6XX_RB_DEPTH_CNTL 0x00008871
-#define A6XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
+#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
#define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
#define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
#define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
@@ -3308,7 +3458,7 @@ static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK;
}
#define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020
-#define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000040
+#define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
#define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080
#define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872
@@ -3819,6 +3969,14 @@ static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val)
return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK;
}
+#define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00
+
+#define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10
+
+#define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20
+
+#define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30
+
#define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00
#define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007
#define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0
@@ -3826,11 +3984,12 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val)
{
return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK;
}
-#define A6XX_RB_2D_BLIT_CNTL_UNK3__MASK 0x00000078
-#define A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT 3
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK3(uint32_t val)
+#define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008
+#define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070
+#define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val)
{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK3__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK3__MASK;
+ return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK;
}
#define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080
#define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00
@@ -3859,11 +4018,11 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val)
{
return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK;
}
-#define A6XX_RB_2D_BLIT_CNTL_UNK29__MASK 0x20000000
-#define A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT 29
-static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK29(uint32_t val)
+#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000
+#define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29
+static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val)
{
- return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK29__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK29__MASK;
+ return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK;
}
#define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01
@@ -3997,11 +4156,17 @@ static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val)
#define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05
#define REG_A6XX_RB_CCU_CNTL 0x00008e07
-#define A6XX_RB_CCU_CNTL_OFFSET__MASK 0xff800000
-#define A6XX_RB_CCU_CNTL_OFFSET__SHIFT 23
-static inline uint32_t A6XX_RB_CCU_CNTL_OFFSET(uint32_t val)
+#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000
+#define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23
+static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val)
{
- return ((val >> 12) << A6XX_RB_CCU_CNTL_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_OFFSET__MASK;
+ return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK;
+}
+#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000
+#define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12
+static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val)
+{
+ return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK;
}
#define A6XX_RB_CCU_CNTL_GMEM 0x00400000
#define A6XX_RB_CCU_CNTL_UNK2 0x00000004
@@ -4052,7 +4217,13 @@ static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val)
return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK;
}
-#define REG_A6XX_VPC_UNKNOWN_9100 0x00009100
+#define REG_A6XX_VPC_GS_PARAM 0x00009100
+#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff
+#define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0
+static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val)
+{
+ return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK;
+}
#define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101
#define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
@@ -4448,10 +4619,16 @@ static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val)
#define REG_A6XX_PC_MODE_CNTL 0x00009804
-#define REG_A6XX_PC_UNKNOWN_9805 0x00009805
+#define REG_A6XX_PC_POWER_CNTL 0x00009805
#define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806
+#define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808
+#define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE 0x00008000
+
+#define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a
+#define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001
+
#define REG_A6XX_PC_DRAW_CMD 0x00009840
#define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff
#define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0
@@ -4543,7 +4720,23 @@ static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val)
return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK;
}
-#define REG_A6XX_PC_PRIMITIVE_CNTL_3 0x00009b03
+#define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03
+#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
+#define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0
+static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val)
+{
+ return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK;
+}
+#define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100
+#define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200
+#define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400
+#define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800
+#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000
+#define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16
+static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val)
+{
+ return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK;
+}
#define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04
#define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff
@@ -4576,6 +4769,7 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val)
{
return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK;
}
+#define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000
#define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16
static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val)
@@ -4763,11 +4957,11 @@ static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val)
}
#define REG_A6XX_VFD_CONTROL_2 0x0000a002
-#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSPATCHID(uint32_t val)
+#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff
+#define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0
+static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val)
{
- return ((val) << A6XX_VFD_CONTROL_2_REGID_HSPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSPATCHID__MASK;
+ return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK;
}
#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00
#define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8
@@ -4777,17 +4971,17 @@ static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val)
}
#define REG_A6XX_VFD_CONTROL_3 0x0000a003
-#define A6XX_VFD_CONTROL_3_UNK0__MASK 0x000000ff
-#define A6XX_VFD_CONTROL_3_UNK0__SHIFT 0
-static inline uint32_t A6XX_VFD_CONTROL_3_UNK0(uint32_t val)
+#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff
+#define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0
+static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val)
{
- return ((val) << A6XX_VFD_CONTROL_3_UNK0__SHIFT) & A6XX_VFD_CONTROL_3_UNK0__MASK;
+ return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK;
}
-#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK 0x0000ff00
-#define A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT 8
-static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPATCHID(uint32_t val)
+#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00
+#define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8
+static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val)
{
- return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPATCHID__MASK;
+ return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK;
}
#define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
#define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
@@ -4828,9 +5022,12 @@ static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val)
#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001
#define REG_A6XX_VFD_MODE_CNTL 0x0000a007
-#define A6XX_VFD_MODE_CNTL_BINNING_PASS 0x00000001
-#define A6XX_VFD_MODE_CNTL_UNK1 0x00000002
-#define A6XX_VFD_MODE_CNTL_UNK2 0x00000004
+#define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007
+#define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0
+static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val)
+{
+ return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK;
+}
#define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008
#define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001
@@ -4913,7 +5110,7 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
}
-#define REG_A6XX_SP_UNKNOWN_A0F8 0x0000a0f8
+#define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8
#define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601
@@ -5091,11 +5288,11 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val)
#define REG_A6XX_SP_VS_INSTRLEN 0x0000a824
#define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825
-#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830
@@ -5201,11 +5398,11 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val)
#define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c
#define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d
-#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840
@@ -5379,11 +5576,11 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val)
#define REG_A6XX_SP_DS_INSTRLEN 0x0000a864
#define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865
-#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870
@@ -5559,11 +5756,11 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val)
#define REG_A6XX_SP_GS_INSTRLEN 0x0000a895
#define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896
-#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0
@@ -5926,11 +6123,11 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val)
#define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8
#define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9
-#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
}
#define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0
@@ -6053,12 +6250,54 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val)
#define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc
#define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd
-#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK 0x0007ffff
-#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT 0
-static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET(uint32_t val)
+#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff
+#define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0
+static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val)
+{
+ return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK;
+}
+
+#define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2
+#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
+#define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0
+static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val)
+{
+ return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK;
+}
+#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00
+#define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8
+static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val)
+{
+ return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK;
+}
+#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000
+#define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16
+static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val)
{
- return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET__MASK;
+ return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK;
}
+#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
+#define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24
+static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val)
+{
+ return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK;
+}
+
+#define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3
+#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff
+#define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0
+static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val)
+{
+ return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK;
+}
+#define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100
+#define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200
+#define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9
+static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val)
+{
+ return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK;
+}
+#define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400
#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0
#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff
@@ -6108,8 +6347,12 @@ static inline uint32_t A6XX_SP_CS_IBO(uint32_t val)
#define REG_A6XX_SP_MODE_CONTROL 0x0000ab00
#define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001
-#define A6XX_SP_MODE_CONTROL_UNK1 0x00000002
-#define A6XX_SP_MODE_CONTROL_UNK2 0x00000004
+#define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006
+#define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1
+static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val)
+{
+ return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK;
+}
#define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008
#define REG_A6XX_SP_FS_CONFIG 0x0000ab04
@@ -6177,7 +6420,7 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
#define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02
-#define REG_A6XX_SP_UNKNOWN_AE03 0x0000ae03
+#define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03
#define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04
#define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008
@@ -6192,6 +6435,8 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val)
static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; }
+#define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
+
#define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180
#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff
#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0
@@ -6357,7 +6602,19 @@ static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val)
return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK;
}
-#define REG_A6XX_SP_TP_UNKNOWN_B309 0x0000b309
+#define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309
+#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003
+#define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0
+static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val)
+{
+ return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK;
+}
+#define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc
+#define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2
+static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val)
+{
+ return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK;
+}
#define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0
#define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
@@ -6499,7 +6756,7 @@ static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val)
return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK;
}
-#define REG_A6XX_TPL1_UNKNOWN_B600 0x0000b600
+#define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600
#define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601
@@ -6687,17 +6944,17 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
}
#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986
-#define A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK 0x000000ff
-#define A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT 0
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK0(uint32_t val)
+#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff
+#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val)
{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK0__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK0__MASK;
+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK;
}
-#define A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK 0x0000ff00
-#define A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT 8
-static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_UNK8(uint32_t val)
+#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00
+#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8
+static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val)
{
- return ((val) << A6XX_HLSQ_CONTROL_5_REG_UNK8__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_UNK8__MASK;
+ return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK;
}
#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987
@@ -6847,6 +7104,16 @@ static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x00
static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_ADDR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; }
+#define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0
+#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f
+#define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0
+static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val)
+{
+ return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK;
+}
+#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020
+#define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040
+
#define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00
#define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff
#define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0
@@ -6943,6 +7210,8 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val)
static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; }
+#define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22
+
#define REG_A6XX_CP_EVENT_START 0x0000d600
#define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff
#define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0
@@ -7021,7 +7290,7 @@ static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val)
}
#define REG_A6XX_TEX_SAMP_1 0x00000001
-#define A6XX_TEX_SAMP_1_UNK0 0x00000001
+#define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
#define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
@@ -7135,7 +7404,7 @@ static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val)
}
#define REG_A6XX_TEX_CONST_2 0x00000002
-#define A6XX_TEX_CONST_2_UNK4 0x00000010
+#define A6XX_TEX_CONST_2_BUFFER 0x00000010
#define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
#define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
@@ -7148,13 +7417,12 @@ static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val)
{
return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK;
}
-#define A6XX_TEX_CONST_2_TYPE__MASK 0x60000000
+#define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000
#define A6XX_TEX_CONST_2_TYPE__SHIFT 29
static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val)
{
return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK;
}
-#define A6XX_TEX_CONST_2_UNK31 0x80000000
#define REG_A6XX_TEX_CONST_3 0x00000003
#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
@@ -7256,104 +7524,6 @@ static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val)
#define REG_A6XX_TEX_CONST_15 0x0000000f
-#define REG_A6XX_IBO_0 0x00000000
-#define A6XX_IBO_0_TILE_MODE__MASK 0x00000003
-#define A6XX_IBO_0_TILE_MODE__SHIFT 0
-static inline uint32_t A6XX_IBO_0_TILE_MODE(enum a6xx_tile_mode val)
-{
- return ((val) << A6XX_IBO_0_TILE_MODE__SHIFT) & A6XX_IBO_0_TILE_MODE__MASK;
-}
-#define A6XX_IBO_0_FMT__MASK 0x3fc00000
-#define A6XX_IBO_0_FMT__SHIFT 22
-static inline uint32_t A6XX_IBO_0_FMT(enum a6xx_format val)
-{
- return ((val) << A6XX_IBO_0_FMT__SHIFT) & A6XX_IBO_0_FMT__MASK;
-}
-
-#define REG_A6XX_IBO_1 0x00000001
-#define A6XX_IBO_1_WIDTH__MASK 0x00007fff
-#define A6XX_IBO_1_WIDTH__SHIFT 0
-static inline uint32_t A6XX_IBO_1_WIDTH(uint32_t val)
-{
- return ((val) << A6XX_IBO_1_WIDTH__SHIFT) & A6XX_IBO_1_WIDTH__MASK;
-}
-#define A6XX_IBO_1_HEIGHT__MASK 0x3fff8000
-#define A6XX_IBO_1_HEIGHT__SHIFT 15
-static inline uint32_t A6XX_IBO_1_HEIGHT(uint32_t val)
-{
- return ((val) << A6XX_IBO_1_HEIGHT__SHIFT) & A6XX_IBO_1_HEIGHT__MASK;
-}
-
-#define REG_A6XX_IBO_2 0x00000002
-#define A6XX_IBO_2_UNK4 0x00000010
-#define A6XX_IBO_2_PITCH__MASK 0x1fffff80
-#define A6XX_IBO_2_PITCH__SHIFT 7
-static inline uint32_t A6XX_IBO_2_PITCH(uint32_t val)
-{
- return ((val) << A6XX_IBO_2_PITCH__SHIFT) & A6XX_IBO_2_PITCH__MASK;
-}
-#define A6XX_IBO_2_TYPE__MASK 0x60000000
-#define A6XX_IBO_2_TYPE__SHIFT 29
-static inline uint32_t A6XX_IBO_2_TYPE(enum a6xx_tex_type val)
-{
- return ((val) << A6XX_IBO_2_TYPE__SHIFT) & A6XX_IBO_2_TYPE__MASK;
-}
-#define A6XX_IBO_2_UNK31 0x80000000
-
-#define REG_A6XX_IBO_3 0x00000003
-#define A6XX_IBO_3_ARRAY_PITCH__MASK 0x00003fff
-#define A6XX_IBO_3_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_IBO_3_ARRAY_PITCH(uint32_t val)
-{
- return ((val >> 12) << A6XX_IBO_3_ARRAY_PITCH__SHIFT) & A6XX_IBO_3_ARRAY_PITCH__MASK;
-}
-#define A6XX_IBO_3_UNK27 0x08000000
-#define A6XX_IBO_3_FLAG 0x10000000
-
-#define REG_A6XX_IBO_4 0x00000004
-#define A6XX_IBO_4_BASE_LO__MASK 0xffffffff
-#define A6XX_IBO_4_BASE_LO__SHIFT 0
-static inline uint32_t A6XX_IBO_4_BASE_LO(uint32_t val)
-{
- return ((val) << A6XX_IBO_4_BASE_LO__SHIFT) & A6XX_IBO_4_BASE_LO__MASK;
-}
-
-#define REG_A6XX_IBO_5 0x00000005
-#define A6XX_IBO_5_BASE_HI__MASK 0x0001ffff
-#define A6XX_IBO_5_BASE_HI__SHIFT 0
-static inline uint32_t A6XX_IBO_5_BASE_HI(uint32_t val)
-{
- return ((val) << A6XX_IBO_5_BASE_HI__SHIFT) & A6XX_IBO_5_BASE_HI__MASK;
-}
-#define A6XX_IBO_5_DEPTH__MASK 0x3ffe0000
-#define A6XX_IBO_5_DEPTH__SHIFT 17
-static inline uint32_t A6XX_IBO_5_DEPTH(uint32_t val)
-{
- return ((val) << A6XX_IBO_5_DEPTH__SHIFT) & A6XX_IBO_5_DEPTH__MASK;
-}
-
-#define REG_A6XX_IBO_6 0x00000006
-
-#define REG_A6XX_IBO_7 0x00000007
-
-#define REG_A6XX_IBO_8 0x00000008
-
-#define REG_A6XX_IBO_9 0x00000009
-#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff
-#define A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
-static inline uint32_t A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
-{
- return ((val >> 4) << A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_IBO_9_FLAG_BUFFER_ARRAY_PITCH__MASK;
-}
-
-#define REG_A6XX_IBO_10 0x0000000a
-#define A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK 0x0000007f
-#define A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT 0
-static inline uint32_t A6XX_IBO_10_FLAG_BUFFER_PITCH(uint32_t val)
-{
- return ((val >> 6) << A6XX_IBO_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_IBO_10_FLAG_BUFFER_PITCH__MASK;
-}
-
#define REG_A6XX_UBO_0 0x00000000
#define A6XX_UBO_0_BASE_LO__MASK 0xffffffff
#define A6XX_UBO_0_BASE_LO__SHIFT 0
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
index 811589215834..4a3230978c0e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index c9389d9fb599..abb037ccc02b 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
Copyright (C) 2013-2021 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
@@ -205,6 +205,11 @@ enum a5xx_address_mode {
ADDR_64B = 1,
};
+enum a5xx_line_mode {
+ BRESENHAM = 0,
+ RECTANGULAR = 1,
+};
+
#define REG_AXXX_CP_RB_BASE 0x000001c0
#define REG_AXXX_CP_RB_CNTL 0x000001c1
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index e832ae4b937a..7aecf920f9b9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -8,21 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14386 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 67699 bytes, from 2021-05-31 20:21:57)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84226 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 112551 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 150713 bytes, from 2021-06-10 22:34:02)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 180049 bytes, from 2021-06-02 21:44:19)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-05-21 19:18:08)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-02-18 16:45:44)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-05-27 20:22:36)
-- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-05-27 20:18:13)
-
-Copyright (C) 2013-2021 by the following authors:
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2020-12-31 19:26:32)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a2xx.xml ( 90810 bytes, from 2021-06-21 15:24:24)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 14609 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 69086 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2021-11-24 23:05:10)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113358 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149512 bytes, from 2022-01-31 23:06:21)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx.xml ( 184954 bytes, from 2022-03-03 16:41:33)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11331 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2021-01-30 18:25:22)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 6038 bytes, from 2021-07-22 15:21:56)
+- /home/robclark/tmp/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2924 bytes, from 2021-07-22 15:21:56)
+
+Copyright (C) 2013-2022 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@@ -299,6 +299,8 @@ enum adreno_pm4_type3_packets {
CP_SET_BIN_DATA5_OFFSET = 46,
CP_SET_CTXSWITCH_IB = 85,
CP_REG_WRITE = 109,
+ CP_START_BIN = 80,
+ CP_END_BIN = 81,
};
enum adreno_state_block {
@@ -438,7 +440,7 @@ enum cp_blit_cmd {
BLIT_OP_SCALE = 3,
};
-enum a6xx_render_mode {
+enum a6xx_marker {
RM6_BYPASS = 1,
RM6_BINNING = 2,
RM6_GMEM = 4,
@@ -2150,13 +2152,13 @@ static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
#define REG_A6XX_CP_SET_MARKER_0 0x00000000
#define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff
#define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0
-static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
+static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val)
{
return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK;
}
#define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
#define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0
-static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_render_mode val)
+static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val)
{
return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK;
}
@@ -2351,5 +2353,13 @@ static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val)
return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK;
}
+#define REG_CP_START_BIN_BIN_COUNT 0x00000000
+
+#define REG_CP_START_BIN_PREFIX_ADDR 0x00000001
+
+#define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003
+
+#define REG_CP_START_BIN_BODY_DWORDS 0x00000004
+
#endif /* ADRENO_PM4_XML */
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 17:04:48 +0100