diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-06-20 13:10:36 +0200 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2023-08-07 23:30:49 +0200 |
| commit | b3ba797e45288e1be33418d3181b40fce816198b (patch) | |
| tree | b0e91cdfb9f2324e4b110507c4b38c57ef9e22c0 /drivers/gpu/drm/msm/adreno | |
| parent | drm/msm/a6xx: Fix misleading comment (diff) | |
| download | linux-b3ba797e45288e1be33418d3181b40fce816198b.tar.xz linux-b3ba797e45288e1be33418d3181b40fce816198b.zip | |
drm/msm/a6xx: Add some missing header definitions
Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL
bitfields.
This may be substituted with a mesa header sync.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543330/
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx.xml.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 2 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 4dc3be6ed45d..1c051535fd4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -1166,6 +1166,9 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f +#define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008 +#define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 +#define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 9ab15d91aced..fcd9eb53baf8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -425,6 +425,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 +#define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 + #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 |