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| author | Vinod Koul <vkoul@kernel.org> | 2022-04-06 11:40:27 +0200 |
|---|---|---|
| committer | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-04-25 23:56:22 +0200 |
| commit | 7e9cc175b159c49cab8805aec70a88314c2b40ed (patch) | |
| tree | 5e596d609f863dd017cc391ae6a6854f1b220d7a /drivers/gpu/drm/msm/msm_drv.h | |
| parent | drm/msm: Add missing num_dspp field documentation (diff) | |
| download | linux-7e9cc175b159c49cab8805aec70a88314c2b40ed.tar.xz linux-7e9cc175b159c49cab8805aec70a88314c2b40ed.zip | |
drm/msm/disp/dpu1: Add support for DSC in topology
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
The panel has been tested only with 2,2,1 configuration, so for
now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Patchwork: https://patchwork.freedesktop.org/patch/480925/
Link: https://lore.kernel.org/r/20220406094031.1027376-11-vkoul@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/msm/msm_drv.h')
| -rw-r--r-- | drivers/gpu/drm/msm/msm_drv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 3db3f1e06306..0eb6890aa156 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -93,12 +93,14 @@ enum msm_event_wait { * @num_enc: number of compression encoder blocks used * @num_intf: number of interfaces the panel is mounted on * @num_dspp: number of dspp blocks used + * @num_dsc: number of Display Stream Compression (DSC) blocks used */ struct msm_display_topology { u32 num_lm; u32 num_enc; u32 num_intf; u32 num_dspp; + u32 num_dsc; }; /* Commit/Event thread specific structure */ |