drm/nouveau/fbcon: convert accel_init() to new push macros

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>

6 files changed, 289 insertions, 0 deletions

diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h
new file mode 100644
index 000000000000..9ab2a22659e4
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl006c.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+    Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+    Permission is hereby granted, free of charge, to any person obtaining a
+    copy of this software and associated documentation files (the "Software"),
+    to deal in the Software without restriction, including without limitation
+    the rights to use, copy, modify, merge, publish, distribute, sublicense,
+    and/or sell copies of the Software, and to permit persons to whom the
+    Software is furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be included in
+    all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl006c_h_
+#define _cl006c_h_
+
+/* fields and values */
+#define NV06C_PUT                                                  (0x00000040)
+#define NV06C_PUT_PTR                                              31:2
+#define NV06C_GET                                                  (0x00000044)
+#define NV06C_GET_PTR                                              31:2
+
+/* dma method descriptor format */
+#define NV06C_METHOD_ADDRESS                                       12:2
+#define NV06C_METHOD_SUBCHANNEL                                    15:13
+#define NV06C_METHOD_COUNT                                         28:18
+#define NV06C_OPCODE                                               31:29
+#define NV06C_OPCODE_METHOD                                        (0x00000000)
+#define NV06C_OPCODE_NONINC_METHOD                                 (0x00000002)
+
+/* dma data format */
+#define NV06C_DATA                                                 31:0
+
+/* dma jump format */
+#define NV06C_OPCODE_JUMP                                          (0x00000001)
+#define NV06C_JUMP_OFFSET                                          28:2
+#endif /* _cl006c_h_ */
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h
new file mode 100644
index 000000000000..27313c7c43cd
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl206e.h
@@ -0,0 +1,35 @@
+/*******************************************************************************
+    Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+    Permission is hereby granted, free of charge, to any person obtaining a
+    copy of this software and associated documentation files (the "Software"),
+    to deal in the Software without restriction, including without limitation
+    the rights to use, copy, modify, merge, publish, distribute, sublicense,
+    and/or sell copies of the Software, and to permit persons to whom the
+    Software is furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be included in
+    all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl206e_h_
+#define _cl206e_h_
+
+/* dma opcode2 format */
+#define NV206E_DMA_OPCODE2                                         1:0
+#define NV206E_DMA_OPCODE2_NONE                                    (0x00000000)
+/* dma jump_long format */
+#define NV206E_DMA_OPCODE2_JUMP_LONG                               (0x00000001)
+#define NV206E_DMA_JUMP_LONG_OFFSET                                31:2
+/* dma call format */
+#define NV206E_DMA_OPCODE2_CALL                                    (0x00000002)
+#define NV206E_DMA_CALL_OFFSET                                     31:2
+#endif /* _cl206e_h_ */
diff --git a/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h b/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h
new file mode 100644
index 000000000000..673d668885bb
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvhw/class/cl906f.h
@@ -0,0 +1,74 @@
+/*******************************************************************************
+    Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+
+    Permission is hereby granted, free of charge, to any person obtaining a
+    copy of this software and associated documentation files (the "Software"),
+    to deal in the Software without restriction, including without limitation
+    the rights to use, copy, modify, merge, publish, distribute, sublicense,
+    and/or sell copies of the Software, and to permit persons to whom the
+    Software is furnished to do so, subject to the following conditions:
+
+    The above copyright notice and this permission notice shall be included in
+    all copies or substantial portions of the Software.
+
+    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+    IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+    THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+    FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+    DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+#ifndef _cl906f_h_
+#define _cl906f_h_
+
+/* fields and values */
+#define NV906F_SEMAPHOREA                                          (0x00000010)
+#define NV906F_SEMAPHOREA_OFFSET_UPPER                                     7:0
+#define NV906F_SEMAPHOREB                                          (0x00000014)
+#define NV906F_SEMAPHOREB_OFFSET_LOWER                                    31:2
+#define NV906F_SEMAPHOREC                                          (0x00000018)
+#define NV906F_SEMAPHOREC_PAYLOAD                                         31:0
+#define NV906F_SEMAPHORED                                          (0x0000001C)
+#define NV906F_SEMAPHORED_OPERATION                                        3:0
+#define NV906F_SEMAPHORED_OPERATION_ACQUIRE                         0x00000001
+#define NV906F_SEMAPHORED_OPERATION_RELEASE                         0x00000002
+#define NV906F_SEMAPHORED_OPERATION_ACQ_GEQ                         0x00000004
+#define NV906F_SEMAPHORED_OPERATION_ACQ_AND                         0x00000008
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH                                 12:12
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_DISABLED                   0x00000000
+#define NV906F_SEMAPHORED_ACQUIRE_SWITCH_ENABLED                    0x00000001
+#define NV906F_SEMAPHORED_RELEASE_WFI                                    20:20
+#define NV906F_SEMAPHORED_RELEASE_WFI_EN                            0x00000000
+#define NV906F_SEMAPHORED_RELEASE_WFI_DIS                           0x00000001
+#define NV906F_SEMAPHORED_RELEASE_SIZE                                   24:24
+#define NV906F_SEMAPHORED_RELEASE_SIZE_16BYTE                       0x00000000
+#define NV906F_SEMAPHORED_RELEASE_SIZE_4BYTE                        0x00000001
+#define NV906F_NON_STALL_INTERRUPT                                 (0x00000020)
+#define NV906F_NON_STALL_INTERRUPT_HANDLE                                 31:0
+#define NV906F_SET_REFERENCE                                       (0x00000050)
+#define NV906F_SET_REFERENCE_COUNT                                        31:0
+
+/* dma method formats */
+#define NV906F_DMA_METHOD_ADDRESS                                  11:0
+#define NV906F_DMA_SUBDEVICE_MASK                                  15:4
+#define NV906F_DMA_METHOD_SUBCHANNEL                               15:13
+#define NV906F_DMA_TERT_OP                                         17:16
+#define NV906F_DMA_TERT_OP_GRP0_INC_METHOD                         (0x00000000)
+#define NV906F_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK                   (0x00000001)
+#define NV906F_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK                 (0x00000002)
+#define NV906F_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK                   (0x00000003)
+#define NV906F_DMA_TERT_OP_GRP2_NON_INC_METHOD                     (0x00000000)
+#define NV906F_DMA_METHOD_COUNT                                    28:16
+#define NV906F_DMA_IMMD_DATA                                       28:16
+#define NV906F_DMA_SEC_OP                                          31:29
+#define NV906F_DMA_SEC_OP_GRP0_USE_TERT                            (0x00000000)
+#define NV906F_DMA_SEC_OP_INC_METHOD                               (0x00000001)
+#define NV906F_DMA_SEC_OP_GRP2_USE_TERT                            (0x00000002)
+#define NV906F_DMA_SEC_OP_NON_INC_METHOD                           (0x00000003)
+#define NV906F_DMA_SEC_OP_IMMD_DATA_METHOD                         (0x00000004)
+#define NV906F_DMA_SEC_OP_ONE_INC                                  (0x00000005)
+#define NV906F_DMA_SEC_OP_RESERVED6                                (0x00000006)
+#define NV906F_DMA_SEC_OP_END_PB_SEGMENT                           (0x00000007)
+#endif /* _cl906f_h_ */
diff --git a/drivers/gpu/drm/nouveau/include/nvif/push006c.h b/drivers/gpu/drm/nouveau/include/nvif/push006c.h
new file mode 100644
index 000000000000..a31c147e72c7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvif/push006c.h
@@ -0,0 +1,73 @@
+#ifndef __NVIF_PUSH006C_H__
+#define __NVIF_PUSH006C_H__
+#include <nvif/push.h>
+
+#include <nvhw/class/cl006c.h>
+
+#ifndef PUSH006C_SUBC
+// Host methods
+#define PUSH006C_SUBC_NV06E	0
+#define PUSH006C_SUBC_NV176E	0
+#define PUSH006C_SUBC_NV826F	0
+
+// ContextSurfaces2d
+#define PUSH006C_SUBC_NV042	0
+#define PUSH006C_SUBC_NV062	0
+
+// ContextClipRectangle
+#define PUSH006C_SUBC_NV019	0
+
+// ContextRop
+#define PUSH006C_SUBC_NV043	0
+
+// ContextPattern
+#define PUSH006C_SUBC_NV044	0
+
+// Misc dodginess...
+#define PUSH006C_SUBC_NV_SW	1
+
+// ImageBlit
+#define PUSH006C_SUBC_NV05F	2
+#define PUSH006C_SUBC_NV09F	2
+
+// GdiRectangleText
+#define PUSH006C_SUBC_NV04A	3
+
+// Twod
+#define PUSH006C_SUBC_NV502D	3
+
+// MemoryToMemoryFormat
+#define PUSH006C_SUBC_NV039	4
+#define PUSH006C_SUBC_NV5039	4
+
+// DmaCopy
+#define PUSH006C_SUBC_NV85B5	4
+
+// Cipher
+#define PUSH006C_SUBC_NV74C1	4
+#endif
+
+#define PUSH_HDR(p,o,n,s,m,c) do {                                        \
+        PUSH_ASSERT(!((s) & ~DRF_MASK(NV06C_METHOD_SUBCHANNEL)), "subc"); \
+        PUSH_ASSERT(!((m) & ~DRF_SMASK(NV06C_METHOD_ADDRESS)), "mthd");   \
+        PUSH_ASSERT(!((c) & ~DRF_MASK(NV06C_METHOD_COUNT)), "count");     \
+        PUSH_DATA__((p), NVVAL_X(NV06C_METHOD_ADDRESS, (m) >> 2) |        \
+			 NVVAL_X(NV06C_METHOD_SUBCHANNEL, (s)) |          \
+			 NVVAL_X(NV06C_METHOD_COUNT, (c)) |               \
+			 NVVAL_X(NV06C_OPCODE, NV06C_OPCODE_##o),         \
+		    " "n" subc %d mthd 0x%04x size %d - %s",              \
+		    (u32)(s), (u32)(m), (u32)(c), __func__);              \
+} while(0)
+
+#define PUSH_MTHD_HDR(p,c,m,n) PUSH_HDR(p, METHOD, "incr", PUSH006C_SUBC_##c, m, n)
+#define PUSH_MTHD_INC 4:4
+#define PUSH_NINC_HDR(p,c,m,n) PUSH_HDR(p, NONINC_METHOD, "ninc", PUSH006C_SUBC_##c, m, n)
+#define PUSH_NINC_INC 0:0
+
+#define PUSH_JUMP(p,o) do {                                         \
+        PUSH_ASSERT(!((o) & ~0x1fffffffcULL), "offset");            \
+	PUSH_DATA__((p), NVVAL_X(NV06C_OPCODE, NV06C_OPCODE_JUMP) | \
+			 NVVAL_X(NV06C_JUMP_OFFSET, (o) >> 2),      \
+		    " jump 0x%08x - %s", (u32)(o), __func__);       \
+} while(0)
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/push206e.h b/drivers/gpu/drm/nouveau/include/nvif/push206e.h
new file mode 100644
index 000000000000..1dfb8a35423e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvif/push206e.h
@@ -0,0 +1,13 @@
+#ifndef __NVIF_PUSH206E_H__
+#define __NVIF_PUSH206E_H__
+#include <nvif/push006c.h>
+
+#include <nvhw/class/cl206e.h>
+
+#define PUSH_CALL(p,o) do {                                         \
+        PUSH_ASSERT(!((o) & ~0xffffffffcULL), "offset");            \
+	PUSH_DATA__((p), NVDEF(NV206E, DMA, OPCODE2, CALL) |        \
+			 NVVAL(NV206E, DMA, CALL_OFFSET, (o) >> 2), \
+		    " call 0x%08x - %s", (u32)(o), __func__);       \
+} while(0)
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvif/push906f.h b/drivers/gpu/drm/nouveau/include/nvif/push906f.h
new file mode 100644
index 000000000000..cc2866bc8b0a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvif/push906f.h
@@ -0,0 +1,48 @@
+#ifndef __NVIF_PUSH906F_H__
+#define __NVIF_PUSH906F_H__
+#include <nvif/push.h>
+
+#include <nvhw/class/cl906f.h>
+
+#ifndef PUSH906F_SUBC
+// Host methods
+#define PUSH906F_SUBC_NV906F	0
+
+// Twod
+#define PUSH906F_SUBC_NV902D	3
+
+// MemoryToMemoryFormat
+#define PUSH906F_SUBC_NV9039	4
+
+// DmaCopy
+#define PUSH906F_SUBC_NV90B5	4
+#define PUSH906F_SUBC_NVA0B5	4
+#endif
+
+#define PUSH_HDR(p,o,n,f,s,m,c) do {                                                \
+        PUSH_ASSERT(!((s) & ~DRF_MASK(NV906F_DMA_METHOD_SUBCHANNEL)), "subc");      \
+        PUSH_ASSERT(!((m) & ~(DRF_MASK(NV906F_DMA_METHOD_ADDRESS) << 2)), "mthd");   \
+        PUSH_ASSERT(!((c) & ~DRF_MASK(NV906F_DMA_METHOD_COUNT)), "count/immd");     \
+        PUSH_DATA__((p), NVVAL(NV906F, DMA, METHOD_ADDRESS, (m) >> 2) |             \
+			 NVVAL(NV906F, DMA, METHOD_SUBCHANNEL, (s)) |               \
+			 NVVAL(NV906F, DMA, METHOD_COUNT, (c)) |                    \
+			 NVDEF(NV906F, DMA, SEC_OP, o),                             \
+		    " "n" subc %d mthd 0x%04x "f" - %s",                            \
+		    (u32)(s), (u32)(m), (u32)(c), __func__);                        \
+} while(0)
+
+#define PUSH_MTHD_INC 4:4
+#define PUSH_MTHD_HDR(p,c,m,n) \
+	PUSH_HDR(p, INC_METHOD, "incr", "size %d", PUSH906F_SUBC_##c, m, n)
+
+#define PUSH_NINC_INC 0:0
+#define PUSH_NINC_HDR(p,c,m,n) \
+	PUSH_HDR(p, NON_INC_METHOD, "ninc", "size %d", PUSH906F_SUBC_##c, m, n)
+
+#define PUSH_IMMD_HDR(p,c,m,n) \
+	PUSH_HDR(p, IMMD_DATA_METHOD, "immd", "data 0x%04x", PUSH906F_SUBC_##c, m, n)
+
+#define PUSH_1INC_INC 4:0
+#define PUSH_1INC_HDR(p,c,m,n) \
+	PUSH_HDR(p, ONE_INC, "oinc", "size %d", PUSH906F_SUBC_##c, m, n)
+#endif