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authorFrancisco Jerez <currojerez@riseup.net>2010-09-28 20:47:58 +0200
committerBen Skeggs <bskeggs@redhat.com>2010-10-05 01:58:43 +0200
commitcd2fb2e9e0a6a3273d353b18e4bdd21cc0482724 (patch)
tree8f356e8abe542f9f873d84a7e4d7845fd0cb2307 /drivers/gpu/drm/nouveau/nv17_tv.c
parentdrm/nv30-nv40: Fix postdivider mask when writing engine/memory PLLs. (diff)
downloadlinux-cd2fb2e9e0a6a3273d353b18e4bdd21cc0482724.tar.xz
linux-cd2fb2e9e0a6a3273d353b18e4bdd21cc0482724.zip
drm/nv0x-nv4x: Leave the 0x40 bit untouched when changing CRE_LCD.
It's an unrelated PLL filtering control bit, leave it alone when changing the CRTC-encoder binding. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv17_tv.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index a3b886166302..28119fd19d03 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -424,9 +424,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
}
if (tv_norm->kind == CTV_ENC_MODE)
- *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
- else
- *cr_lcd = 0;
+ *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
/* Set the DACCLK register */
dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;