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authorAlex Deucher <alexander.deucher@amd.com>2013-01-19 00:55:54 +0100
committerAlex Deucher <alexander.deucher@amd.com>2013-01-31 22:24:53 +0100
commita65a4369f7a69281b65ed42b7fa2a8e8d6ff585f (patch)
treef4bc2425e3e58ef45d9716d721026c84009889a2 /drivers/gpu/drm/radeon/evergreend.h
parentdrm/radeon: use status regs to determine what to reset (6xx/7xx) (diff)
downloadlinux-a65a4369f7a69281b65ed42b7fa2a8e8d6ff585f.tar.xz
linux-a65a4369f7a69281b65ed42b7fa2a8e8d6ff585f.zip
drm/radeon: use status regs to determine what to reset (evergreen)
When we attempt the reset the GPU, look at the status registers to determine what blocks need to be reset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 5ad29f3fc722..982d25ad9af3 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -729,6 +729,18 @@
#define WAIT_UNTIL 0x8040
#define SRBM_STATUS 0x0E50
+#define RLC_RQ_PENDING (1 << 3)
+#define GRBM_RQ_PENDING (1 << 5)
+#define VMC_BUSY (1 << 8)
+#define MCB_BUSY (1 << 9)
+#define MCB_NON_DISPLAY_BUSY (1 << 10)
+#define MCC_BUSY (1 << 11)
+#define MCD_BUSY (1 << 12)
+#define SEM_BUSY (1 << 14)
+#define RLC_BUSY (1 << 15)
+#define IH_BUSY (1 << 17)
+#define SRBM_STATUS2 0x0EC4
+#define DMA_BUSY (1 << 5)
#define SRBM_SOFT_RESET 0x0E60
#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
#define SOFT_RESET_BIF (1 << 1)