diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2008-10-17 01:21:45 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2008-10-17 23:10:54 +0200 |
| commit | edc6f389f6ae9cb7621270a8ddbb1892bd8df125 (patch) | |
| tree | 775537e224e7eb83290df07779b3e3ab6876adab /drivers/gpu/drm/radeon/radeon_cp.c | |
| parent | radeon: add RS400 family support. (diff) | |
| download | linux-edc6f389f6ae9cb7621270a8ddbb1892bd8df125.tar.xz linux-edc6f389f6ae9cb7621270a8ddbb1892bd8df125.zip | |
radeon: fix PCI bus mastering support enables.
Someone noticed these registers moved around for later chips,
so we redo the codepaths per-chip. PCIE chips don't appear to
require explicit enables.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_cp.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_cp.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index a83d7615ba7f..59a2132a8f57 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -363,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv) R300_cp_microcode[i][0]); } } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) || ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) { DRM_INFO("Loading R400 Microcode\n"); for (i = 0; i < 256; i++) { @@ -652,8 +653,18 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7); /* Turn on bus mastering */ - tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; - RADEON_WRITE(RADEON_BUS_CNTL, tmp); + if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || + ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) { + /* rs400, rs690/rs740 */ + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS; + RADEON_WRITE(RADEON_BUS_CNTL, tmp); + } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) || + ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) { + /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */ + tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; + RADEON_WRITE(RADEON_BUS_CNTL, tmp); + } /* PCIE cards appears to not need this */ dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0; RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame); @@ -1719,6 +1730,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) case CHIP_R300: case CHIP_R350: case CHIP_R420: + case CHIP_R423: case CHIP_RV410: case CHIP_RV515: case CHIP_R520: |