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authorAlex Deucher <alexdeucher@gmail.com>2011-05-20 10:34:17 +0200
committerDave Airlie <airlied@redhat.com>2011-05-20 12:02:22 +0200
commit86a94defe2b88380c28547d7053633b26a397d42 (patch)
tree5f18745f77235b364f85c8b74804957b285cca4e /drivers/gpu/drm/radeon/radeon_encoders.c
parentdrm/radeon/kms: spread spectrum fixes (diff)
downloadlinux-86a94defe2b88380c28547d7053633b26a397d42.tar.xz
linux-86a94defe2b88380c28547d7053633b26a397d42.zip
drm/radeon/kms: fix up DP clock programming on DCE4/5
In DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, depending on the asic. The crtc virtual pixel clock is derived from the DP ref clock. - DCE4: PPLL or ext clock - DCE5: DCPLL or ext clock Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip PPLL/DCPLL programming and only program the DP DTO for the crtc virtual pixel clock. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_encoders.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 6c6793e6e3a5..4d66e249e1c1 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -988,11 +988,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
}
if (ASIC_IS_DCE5(rdev)) {
- if (is_dp && rdev->clock.dp_extclk)
- args.v4.acConfig.ucRefClkSource = 3; /* external src */
- else
+ /* On DCE5 DCPLL usually generates the DP ref clock */
+ if (is_dp) {
+ if (rdev->clock.dp_extclk)
+ args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
+ else
+ args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
+ } else
args.v4.acConfig.ucRefClkSource = pll_id;
} else {
+ /* On DCE4, if there is an external clock, it generates the DP ref clock */
if (is_dp && rdev->clock.dp_extclk)
args.v3.acConfig.ucRefClkSource = 2; /* external src */
else