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authorAlex Deucher <alexdeucher@gmail.com>2009-12-09 23:44:25 +0100
committerDave Airlie <airlied@redhat.com>2009-12-10 06:09:05 +0100
commitb27b63750d912e80d61d2120c4a1664062d0f808 (patch)
treed419533d2b4c7fec1cf4ad89485da755347a33fb /drivers/gpu/drm/radeon/radeon_mode.h
parentdrm/radeon/kms/avivo: fix some bugs in the display bandwidth setup (diff)
downloadlinux-b27b63750d912e80d61d2120c4a1664062d0f808.tar.xz
linux-b27b63750d912e80d61d2120c4a1664062d0f808.zip
drm/radeon/kms/avivo: add support for new pll selection algo
Supported on all AVIVO-based asics. Can be disabled via the new_pll module parameter: new_pll=0 - disable new_pll=1 - enable enabled by default [airlied: fixed to use do_div] Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to '')
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 15ec7ca18a95..44d4b652ea12 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -437,6 +437,15 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
uint32_t *post_div_p,
int flags);
+extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
+ uint64_t freq,
+ uint32_t *dot_clock_p,
+ uint32_t *fb_div_p,
+ uint32_t *frac_fb_div_p,
+ uint32_t *ref_div_p,
+ uint32_t *post_div_p,
+ int flags);
+
extern void radeon_setup_encoder_clones(struct drm_device *dev);
struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);