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| author | Alex Deucher <alexander.deucher@amd.com> | 2013-04-17 15:35:39 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-04-22 16:39:09 +0200 |
| commit | e884fc640ccbdb6f94b9bdb57cfb8464b6688f4c (patch) | |
| tree | 090414175b00344c145e5d3b4de4874e8c855441 /drivers/gpu/drm/radeon/rv515.c | |
| parent | drm/radeon: properly lock disp in mc_stop/resume for evergreen+ (diff) | |
| download | linux-e884fc640ccbdb6f94b9bdb57cfb8464b6688f4c.tar.xz linux-e884fc640ccbdb6f94b9bdb57cfb8464b6688f4c.zip | |
drm/radeon: disable the crtcs in mc_stop (r5xx-r7xx) (v2)
Just disabling the mem requests should be enough, but
that doesn't seem to work correctly on efi systems.
v2: blank displays first, then disable.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/rv515.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/rv515.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c index 6a1e5dd5b5ee..ffcba730c57c 100644 --- a/drivers/gpu/drm/radeon/rv515.c +++ b/drivers/gpu/drm/radeon/rv515.c @@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { radeon_wait_for_vblank(rdev, i); + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); } /* wait for the next frame */ frame_count = radeon_get_vblank_counter(rdev, i); @@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save) break; udelay(1); } + + /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); + tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); + tmp &= ~AVIVO_CRTC_EN; + WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); + WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); + save->crtc_enabled[i] = false; + /* ***** */ } else { save->crtc_enabled[i] = false; } |