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author | Alex Deucher <alexdeucher@gmail.com> | 2010-06-04 19:10:12 +0200 |
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committer | Dave Airlie <airlied@redhat.com> | 2010-08-02 02:00:05 +0200 |
commit | e7aeeba6a8fb86ac52bcffa0b72942f784f2b37f (patch) | |
tree | 889d8196e31ec490beba8b801236d7734e8d36bb /drivers/gpu/drm/radeon/rv770.c | |
parent | drm/radeon/kms: fix CS alignment checking for tiling (v2) (diff) | |
download | linux-e7aeeba6a8fb86ac52bcffa0b72942f784f2b37f.tar.xz linux-e7aeeba6a8fb86ac52bcffa0b72942f784f2b37f.zip |
drm/radeon/kms/r6xx+: add query for tile config (v2)
Userspace needs this information to access tiled
buffers via the CPU.
v2: rebased on evergreen accel changes
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/rv770.c')
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index 836c15ab84d1..236fe6681922 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c @@ -674,8 +674,9 @@ static void rv770_gpu_init(struct radeon_device *rdev) r600_count_pipe_bits((cc_rb_backend_disable & R7XX_MAX_BACKENDS_MASK) >> 16)), (cc_rb_backend_disable >> 16)); - gb_tiling_config |= BACKEND_MAP(backend_map); + rdev->config.rv770.tile_config = gb_tiling_config; + gb_tiling_config |= BACKEND_MAP(backend_map); WREG32(GB_TILING_CONFIG, gb_tiling_config); WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |