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authorMarek Olšák <marek.olsak@amd.com>2016-10-10 13:23:25 +0200
committerAlex Deucher <alexander.deucher@amd.com>2016-10-12 21:44:15 +0200
commit113d0f9db7be5a3038d9800ea1dddfb373c2b5a6 (patch)
tree95ecb1c469116b1636a61609d468ffba993bb256 /drivers/gpu/drm/radeon/si.c
parentdrm/amdgpu: initialize the context reset_counter in amdgpu_ctx_init (diff)
downloadlinux-113d0f9db7be5a3038d9800ea1dddfb373c2b5a6.tar.xz
linux-113d0f9db7be5a3038d9800ea1dddfb373c2b5a6.zip
drm/radeon: allow TA_CS_BC_BASE_ADDR on SI
Required for border colors in compute shaders. Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7ee9aafbdf74..e402be8821c4 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -4431,6 +4431,7 @@ static bool si_vm_reg_valid(u32 reg)
case SPI_CONFIG_CNTL:
case SPI_CONFIG_CNTL_1:
case TA_CNTL_AUX:
+ case TA_CS_BC_BASE_ADDR:
return true;
default:
DRM_ERROR("Invalid register 0x%x in CS\n", reg);