diff options
author | Dave Airlie <airlied@redhat.com> | 2017-06-16 01:54:02 +0200 |
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committer | Dave Airlie <airlied@redhat.com> | 2017-06-16 01:56:53 +0200 |
commit | 04d4fb5fa63876d8e7cf67f2788aecfafc6a28a7 (patch) | |
tree | 92aec67d7b5a1359baff1a508d381234f046743e /drivers/gpu/drm/radeon | |
parent | Merge tag 'drm-misc-next-2017-06-15' of git://anongit.freedesktop.org/git/drm... (diff) | |
parent | drm/amdgpu: Fix compiler warnings (diff) | |
download | linux-04d4fb5fa63876d8e7cf67f2788aecfafc6a28a7.tar.xz linux-04d4fb5fa63876d8e7cf67f2788aecfafc6a28a7.zip |
Merge branch 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux into drm-next
New radeon and amdgpu features for 4.13:
- Lots of Vega10 bug fixes
- Preliminary Raven support
- KIQ support for compute rings
- MEC queue management rework from Andres
- Audio support for DCE6
- SR-IOV improvements
- Improved module parameters for controlling radeon vs amdgpu support
for SI and CIK
- Bug fixes
- General code cleanups
[airlied: dropped drmP.h header from one file was needed and build broke]
* 'drm-next-4.13' of git://people.freedesktop.org/~agd5f/linux: (362 commits)
drm/amdgpu: Fix compiler warnings
drm/amdgpu: vm_update_ptes remove code duplication
drm/amd/amdgpu: Port VCN over to new SOC15 macros
drm/amd/amdgpu: Port PSP v10.0 over to new SOC15 macros
drm/amd/amdgpu: Port PSP v3.1 over to new SOC15 macros
drm/amd/amdgpu: Port NBIO v7.0 driver over to new SOC15 macros
drm/amd/amdgpu: Port NBIO v6.1 driver over to new SOC15 macros
drm/amd/amdgpu: Port UVD 7.0 over to new SOC15 macros
drm/amd/amdgpu: Port MMHUB over to new SOC15 macros
drm/amd/amdgpu: Cleanup gfxhub read-modify-write patterns
drm/amd/amdgpu: Port GFXHUB over to new SOC15 macros
drm/amd/amdgpu: Add offset variant to SOC15 macros
drm/amd/powerplay: add avfs control for Vega10
drm/amdgpu: add virtual display support for raven
drm/amdgpu/gfx9: fix compute ring doorbell index
drm/amd/amdgpu: Rename KIQ ring to avoid spaces
drm/amd/amdgpu: gfx9 tidy ups (v2)
drm/amdgpu: add contiguous flag in ucode bo create
drm/amdgpu: fix missed gpu info firmware when cache firmware during S3
drm/amdgpu: export test ib debugfs interface
...
Diffstat (limited to 'drivers/gpu/drm/radeon')
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 27 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 943 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_irq_kms.c | 35 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_kfd.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_kms.c | 25 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/si.c | 655 |
8 files changed, 412 insertions, 1344 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 258912132b62..4074805034da 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -4580,23 +4580,24 @@ static int cik_cp_compute_resume(struct radeon_device *rdev) /* init the pipes */ mutex_lock(&rdev->srbm_mutex); - eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr; + for (i = 0; i < rdev->mec.num_pipe; ++i) { + cik_srbm_select(rdev, 0, i, 0, 0); - cik_srbm_select(rdev, 0, 0, 0, 0); - - /* write the EOP addr */ - WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); - WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); + eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2) ; + /* write the EOP addr */ + WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); + WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); - /* set the VMID assigned */ - WREG32(CP_HPD_EOP_VMID, 0); + /* set the VMID assigned */ + WREG32(CP_HPD_EOP_VMID, 0); - /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ - tmp = RREG32(CP_HPD_EOP_CONTROL); - tmp &= ~EOP_SIZE_MASK; - tmp |= order_base_2(MEC_HPD_SIZE / 8); - WREG32(CP_HPD_EOP_CONTROL, tmp); + /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ + tmp = RREG32(CP_HPD_EOP_CONTROL); + tmp &= ~EOP_SIZE_MASK; + tmp |= order_base_2(MEC_HPD_SIZE / 8); + WREG32(CP_HPD_EOP_CONTROL, tmp); + } mutex_unlock(&rdev->srbm_mutex); /* init the queues. Just two for now. */ diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 0bf103536404..44527e679d31 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -35,6 +35,10 @@ #include "evergreen_blit_shaders.h" #include "radeon_ucode.h" +#define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc)) +#define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc)) +#define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc)) + /* * Indirect registers accessor */ @@ -1714,38 +1718,10 @@ void evergreen_pm_finish(struct radeon_device *rdev) */ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) { - bool connected = false; - - switch (hpd) { - case RADEON_HPD_1: - if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case RADEON_HPD_2: - if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case RADEON_HPD_3: - if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case RADEON_HPD_4: - if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case RADEON_HPD_5: - if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - case RADEON_HPD_6: - if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) - connected = true; - break; - default: - break; - } + if (hpd == RADEON_HPD_NONE) + return false; - return connected; + return !!(RREG32(DC_HPDx_INT_STATUS_REG(hpd)) & DC_HPDx_SENSE); } /** @@ -1759,61 +1735,15 @@ bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) void evergreen_hpd_set_polarity(struct radeon_device *rdev, enum radeon_hpd_id hpd) { - u32 tmp; bool connected = evergreen_hpd_sense(rdev, hpd); - switch (hpd) { - case RADEON_HPD_1: - tmp = RREG32(DC_HPD1_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD1_INT_CONTROL, tmp); - break; - case RADEON_HPD_2: - tmp = RREG32(DC_HPD2_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD2_INT_CONTROL, tmp); - break; - case RADEON_HPD_3: - tmp = RREG32(DC_HPD3_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD3_INT_CONTROL, tmp); - break; - case RADEON_HPD_4: - tmp = RREG32(DC_HPD4_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD4_INT_CONTROL, tmp); - break; - case RADEON_HPD_5: - tmp = RREG32(DC_HPD5_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD5_INT_CONTROL, tmp); - break; - case RADEON_HPD_6: - tmp = RREG32(DC_HPD6_INT_CONTROL); - if (connected) - tmp &= ~DC_HPDx_INT_POLARITY; - else - tmp |= DC_HPDx_INT_POLARITY; - WREG32(DC_HPD6_INT_CONTROL, tmp); - break; - default: - break; - } + if (hpd == RADEON_HPD_NONE) + return; + + if (connected) + WREG32_AND(DC_HPDx_INT_CONTROL(hpd), ~DC_HPDx_INT_POLARITY); + else + WREG32_OR(DC_HPDx_INT_CONTROL(hpd), DC_HPDx_INT_POLARITY); } /** @@ -1833,7 +1763,8 @@ void evergreen_hpd_init(struct radeon_device *rdev) DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct radeon_connector *radeon_connector = to_radeon_connector(connector); + enum radeon_hpd_id hpd = + to_radeon_connector(connector)->hpd.hpd; if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { @@ -1844,31 +1775,14 @@ void evergreen_hpd_init(struct radeon_device *rdev) */ continue; } - switch (radeon_connector->hpd.hpd) { - case RADEON_HPD_1: - WREG32(DC_HPD1_CONTROL, tmp); - break; - case RADEON_HPD_2: - WREG32(DC_HPD2_CONTROL, tmp); - break; - case RADEON_HPD_3: - WREG32(DC_HPD3_CONTROL, tmp); - break; - case RADEON_HPD_4: - WREG32(DC_HPD4_CONTROL, tmp); - break; - case RADEON_HPD_5: - WREG32(DC_HPD5_CONTROL, tmp); - break; - case RADEON_HPD_6: - WREG32(DC_HPD6_CONTROL, tmp); - break; - default: - break; - } - radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); - if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) - enabled |= 1 << radeon_connector->hpd.hpd; + + if (hpd == RADEON_HPD_NONE) + continue; + + WREG32(DC_HPDx_CONTROL(hpd), tmp); + enabled |= 1 << hpd; + + radeon_hpd_set_polarity(rdev, hpd); } radeon_irq_kms_enable_hpd(rdev, enabled); } @@ -1888,31 +1802,14 @@ void evergreen_hpd_fini(struct radeon_device *rdev) unsigned disabled = 0; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct radeon_connector *radeon_connector = to_radeon_connector(connector); - switch (radeon_connector->hpd.hpd) { - case RADEON_HPD_1: - WREG32(DC_HPD1_CONTROL, 0); - break; - case RADEON_HPD_2: - WREG32(DC_HPD2_CONTROL, 0); - break; - case RADEON_HPD_3: - WREG32(DC_HPD3_CONTROL, 0); - break; - case RADEON_HPD_4: - WREG32(DC_HPD4_CONTROL, 0); - break; - case RADEON_HPD_5: - WREG32(DC_HPD5_CONTROL, 0); - break; - case RADEON_HPD_6: - WREG32(DC_HPD6_CONTROL, 0); - break; - default: - break; - } - if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) - disabled |= 1 << radeon_connector->hpd.hpd; + enum radeon_hpd_id hpd = + to_radeon_connector(connector)->hpd.hpd; + + if (hpd == RADEON_HPD_NONE) + continue; + + WREG32(DC_HPDx_CONTROL(hpd), 0); + disabled |= 1 << hpd; } radeon_irq_kms_disable_hpd(rdev, disabled); } @@ -2637,6 +2534,15 @@ static const unsigned evergreen_dp_offsets[] = EVERGREEN_DP5_REGISTER_OFFSET }; +static const unsigned evergreen_disp_int_status[] = +{ + DISP_INTERRUPT_STATUS, + DISP_INTERRUPT_STATUS_CONTINUE, + DISP_INTERRUPT_STATUS_CONTINUE2, + DISP_INTERRUPT_STATUS_CONTINUE3, + DISP_INTERRUPT_STATUS_CONTINUE4, + DISP_INTERRUPT_STATUS_CONTINUE5 +}; /* * Assumption is that EVERGREEN_CRTC_MASTER_EN enable for requested crtc @@ -4543,6 +4449,7 @@ u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) void evergreen_disable_interrupt_state(struct radeon_device *rdev) { + int i; u32 tmp; if (rdev->family >= CHIP_CAYMAN) { @@ -4558,56 +4465,27 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) WREG32(DMA_CNTL, tmp); WREG32(GRBM_INT_CNTL, 0); WREG32(SRBM_INT_CNTL, 0); - WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); - if (rdev->num_crtc >= 4) { - WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 6) { - WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); - } - - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); - if (rdev->num_crtc >= 4) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 6) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); - } + for (i = 0; i < rdev->num_crtc; i++) + WREG32(INT_MASK + crtc_offsets[i], 0); + for (i = 0; i < rdev->num_crtc; i++) + WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); /* only one DAC on DCE5 */ if (!ASIC_IS_DCE5(rdev)) WREG32(DACA_AUTODETECT_INT_CONTROL, 0); WREG32(DACB_AUTODETECT_INT_CONTROL, 0); - tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD1_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD2_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD3_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD4_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD5_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD6_INT_CONTROL, tmp); - + for (i = 0; i < 6; i++) + WREG32_AND(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_POLARITY); } +/* Note that the order we write back regs here is important */ int evergreen_irq_set(struct radeon_device *rdev) { + int i; u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; - u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; - u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; u32 grbm_int_cntl = 0; - u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; u32 dma_cntl, dma_cntl1 = 0; u32 thermal_int = 0; @@ -4623,12 +4501,6 @@ int evergreen_irq_set(struct radeon_device *rdev) return 0; } - hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); if (rdev->family == CHIP_ARUBA) thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); @@ -4636,13 +4508,6 @@ int evergreen_irq_set(struct radeon_device *rdev) thermal_int = RREG32(CG_THERMAL_INT) & ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); - afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK; - dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; if (rdev->family >= CHIP_CAYMAN) { @@ -4685,85 +4550,6 @@ int evergreen_irq_set(struct radeon_device *rdev) thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; } - if (rdev->irq.crtc_vblank_int[0] || - atomic_read(&rdev->irq.pflip[0])) { - DRM_DEBUG("evergreen_irq_set: vblank 0\n"); - crtc1 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[1] || - atomic_read(&rdev->irq.pflip[1])) { - DRM_DEBUG("evergreen_irq_set: vblank 1\n"); - crtc2 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[2] || - atomic_read(&rdev->irq.pflip[2])) { - DRM_DEBUG("evergreen_irq_set: vblank 2\n"); - crtc3 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[3] || - atomic_read(&rdev->irq.pflip[3])) { - DRM_DEBUG("evergreen_irq_set: vblank 3\n"); - crtc4 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[4] || - atomic_read(&rdev->irq.pflip[4])) { - DRM_DEBUG("evergreen_irq_set: vblank 4\n"); - crtc5 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[5] || - atomic_read(&rdev->irq.pflip[5])) { - DRM_DEBUG("evergreen_irq_set: vblank 5\n"); - crtc6 |= VBLANK_INT_MASK; - } - if (rdev->irq.hpd[0]) { - DRM_DEBUG("evergreen_irq_set: hpd 1\n"); - hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[1]) { - DRM_DEBUG("evergreen_irq_set: hpd 2\n"); - hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[2]) { - DRM_DEBUG("evergreen_irq_set: hpd 3\n"); - hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[3]) { - DRM_DEBUG("evergreen_irq_set: hpd 4\n"); - hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[4]) { - DRM_DEBUG("evergreen_irq_set: hpd 5\n"); - hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[5]) { - DRM_DEBUG("evergreen_irq_set: hpd 6\n"); - hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.afmt[0]) { - DRM_DEBUG("evergreen_irq_set: hdmi 0\n"); - afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->irq.afmt[1]) { - DRM_DEBUG("evergreen_irq_set: hdmi 1\n"); - afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->irq.afmt[2]) { - DRM_DEBUG("evergreen_irq_set: hdmi 2\n"); - afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->irq.afmt[3]) { - DRM_DEBUG("evergreen_irq_set: hdmi 3\n"); - afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->irq.afmt[4]) { - DRM_DEBUG("evergreen_irq_set: hdmi 4\n"); - afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->irq.afmt[5]) { - DRM_DEBUG("evergreen_irq_set: hdmi 5\n"); - afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK; - } - if (rdev->family >= CHIP_CAYMAN) { cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); @@ -4778,51 +4564,35 @@ int evergreen_irq_set(struct radeon_device *rdev) WREG32(GRBM_INT_CNTL, grbm_int_cntl); - WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); - WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); - if (rdev->num_crtc >= 4) { - WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); - WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); - } - if (rdev->num_crtc >= 6) { - WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); - WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); - } - - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - if (rdev->num_crtc >= 4) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - } - if (rdev->num_crtc >= 6) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - } - - WREG32(DC_HPD1_INT_CONTROL, hpd1); - WREG32(DC_HPD2_INT_CONTROL, hpd2); - WREG32(DC_HPD3_INT_CONTROL, hpd3); - WREG32(DC_HPD4_INT_CONTROL, hpd4); - WREG32(DC_HPD5_INT_CONTROL, hpd5); - WREG32(DC_HPD6_INT_CONTROL, hpd6); + for (i = 0; i < rdev->num_crtc; i++) { + radeon_irq_kms_set_irq_n_enabled( + rdev, INT_MASK + crtc_offsets[i], + VBLANK_INT_MASK, + rdev->irq.crtc_vblank_int[i] || + atomic_read(&rdev->irq.pflip[i]), "vblank", i); + } + + for (i = 0; i < rdev->num_crtc; i++) + WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); + + for (i = 0; i < 6; i++) { + radeon_irq_kms_set_irq_n_enabled( + rdev, DC_HPDx_INT_CONTROL(i), + DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN, + rdev->irq.hpd[i], "HPD", i); + } + if (rdev->family == CHIP_ARUBA) WREG32(TN_CG_THERMAL_INT_CTRL, thermal_int); else WREG32(CG_THERMAL_INT, thermal_int); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5); - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6); + for (i = 0; i < 6; i++) { + radeon_irq_kms_set_irq_n_enabled( + rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], + AFMT_AZ_FORMAT_WTRIG_MASK, + rdev->irq.afmt[i], "HDMI", i); + } /* posting read */ RREG32(SRBM_STATUS); @@ -4830,168 +4600,53 @@ int evergreen_irq_set(struct radeon_device *rdev) return 0; } +/* Note that the order we write back regs here is important */ static void evergreen_irq_ack(struct radeon_device *rdev) { - u32 tmp; + int i, j; + u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; + u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; + u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; - rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); - rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); - rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); - rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); - rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); - rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); - rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); - if (rdev->num_crtc >= 4) { - rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); - } - if (rdev->num_crtc >= 6) { - rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); - } - - rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); - - if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); - - if (rdev->num_crtc >= 4) { - if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); - } - - if (rdev->num_crtc >= 6) { - if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); - } - - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { - tmp = RREG32(DC_HPD1_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD1_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { - tmp = RREG32(DC_HPD2_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD2_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { - tmp = RREG32(DC_HPD3_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD3_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { - tmp = RREG32(DC_HPD4_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD4_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { - tmp = RREG32(DC_HPD5_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD5_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { - tmp = RREG32(DC_HPD6_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD6_INT_CONTROL, tmp); - } - - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { - tmp = RREG32(DC_HPD1_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD1_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { - tmp = RREG32(DC_HPD2_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD2_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { - tmp = RREG32(DC_HPD3_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD3_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { - tmp = RREG32(DC_HPD4_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD4_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { - tmp = RREG32(DC_HPD5_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD5_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { - tmp = RREG32(DC_HPD6_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD6_INT_CONTROL, tmp); - } - - if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); - } - if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); - } - if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); - } - if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); - } - if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); - } - if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) { - tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); - tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; - WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); + for (i = 0; i < 6; i++) { + disp_int[i] = RREG32(evergreen_disp_int_status[i]); + afmt_status[i] = RREG32(AFMT_STATUS + crtc_offsets[i]); + if (i < rdev->num_crtc) + grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); + } + + /* We write back each interrupt register in pairs of two */ + for (i = 0; i < rdev->num_crtc; i += 2) { + for (j = i; j < (i + 2); j++) { + if (grph_int[j] & GRPH_PFLIP_INT_OCCURRED) + WREG32(GRPH_INT_STATUS + crtc_offsets[j], + GRPH_PFLIP_INT_CLEAR); + } + + for (j = i; j < (i + 2); j++) { + if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) + WREG32(VBLANK_STATUS + crtc_offsets[j], + VBLANK_ACK); + if (disp_int[j] & LB_D1_VLINE_INTERRUPT) + WREG32(VLINE_STATUS + crtc_offsets[j], + VLINE_ACK); + } + } + + for (i = 0; i < 6; i++) { + if (disp_int[i] & DC_HPD1_INTERRUPT) + WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); + } + + for (i = 0; i < 6; i++) { + if (disp_int[i] & DC_HPD1_RX_INTERRUPT) + WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); + } + + for (i = 0; i < 6; i++) { + if (afmt_status[i] & AFMT_AZ_FORMAT_WTRIG) + WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], + AFMT_AZ_FORMAT_WTRIG_ACK); } } @@ -5037,6 +4692,10 @@ static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) int evergreen_irq_process(struct radeon_device *rdev) { + u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; + u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; + u32 crtc_idx, hpd_idx, afmt_idx; + u32 mask; u32 wptr; u32 rptr; u32 src_id, src_data; @@ -5046,6 +4705,7 @@ int evergreen_irq_process(struct radeon_device *rdev) bool queue_dp = false; bool queue_thermal = false; u32 status, addr; + const char *event_name; if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE; @@ -5074,184 +4734,44 @@ restart_ih: switch (src_id) { case 1: /* D1 vblank/vline */ - switch (src_data) { - case 0: /* D1 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D1 vblank - IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[0]) { - drm_handle_vblank(rdev->ddev, 0); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[0])) - radeon_crtc_handle_vblank(rdev, 0); - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D1 vblank\n"); - - break; - case 1: /* D1 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D1 vline - IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; - DRM_DEBUG("IH: D1 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 2: /* D2 vblank/vline */ - switch (src_data) { - case 0: /* D2 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D2 vblank - IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[1]) { - drm_handle_vblank(rdev->ddev, 1); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[1])) - radeon_crtc_handle_vblank(rdev, 1); - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D2 vblank\n"); - - break; - case 1: /* D2 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D2 vline - IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; - DRM_DEBUG("IH: D2 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 3: /* D3 vblank/vline */ - switch (src_data) { - case 0: /* D3 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D3 vblank - IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[2]) { - drm_handle_vblank(rdev->ddev, 2); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[2])) - radeon_crtc_handle_vblank(rdev, 2); - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D3 vblank\n"); - - break; - case 1: /* D3 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D3 vline - IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; - DRM_DEBUG("IH: D3 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 4: /* D4 vblank/vline */ - switch (src_data) { - case 0: /* D4 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D4 vblank - IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[3]) { - drm_handle_vblank(rdev->ddev, 3); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[3])) - radeon_crtc_handle_vblank(rdev, 3); - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D4 vblank\n"); - - break; - case 1: /* D4 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D4 vline - IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; - DRM_DEBUG("IH: D4 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 5: /* D5 vblank/vline */ - switch (src_data) { - case 0: /* D5 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D5 vblank - IH event w/o asserted irq bit?\n"); + case 6: /* D6 vblank/vline */ + crtc_idx = src_id - 1; + + if (src_data == 0) { /* vblank */ + mask = LB_D1_VBLANK_INTERRUPT; + event_name = "vblank"; - if (rdev->irq.crtc_vblank_int[4]) { - drm_handle_vblank(rdev->ddev, 4); + if (rdev->irq.crtc_vblank_int[crtc_idx]) { + drm_handle_vblank(rdev->ddev, crtc_idx); rdev->pm.vblank_sync = true; wake_up(&rdev->irq.vblank_queue); } - if (atomic_read(&rdev->irq.pflip[4])) - radeon_crtc_handle_vblank(rdev, 4); - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D5 vblank\n"); - - break; - case 1: /* D5 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D5 vline - IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; - DRM_DEBUG("IH: D5 vline\n"); + if (atomic_read(&rdev->irq.pflip[crtc_idx])) { + radeon_crtc_handle_vblank(rdev, + crtc_idx); + } - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + } else if (src_data == 1) { /* vline */ + mask = LB_D1_VLINE_INTERRUPT; + event_name = "vline"; + } else { + DRM_DEBUG("Unhandled interrupt: %d %d\n", + src_id, src_data); break; } - break; - case 6: /* D6 vblank/vline */ - switch (src_data) { - case 0: /* D6 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: D6 vblank - IH event w/o asserted irq bit?\n"); - if (rdev->irq.crtc_vblank_int[5]) { - drm_handle_vblank(rdev->ddev, 5); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[5])) - radeon_crtc_handle_vblank(rdev, 5); - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D6 vblank\n"); - - break; - case 1: /* D6 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) - DRM_DEBUG("IH: D6 vline - IH event w/o asserted irq bit?\n"); + if (!(disp_int[crtc_idx] & mask)) { + DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n", + crtc_idx + 1, event_name); + } - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; - DRM_DEBUG("IH: D6 vline\n"); + disp_int[crtc_idx] &= ~mask; + DRM_DEBUG("IH: D%d %s\n", crtc_idx + 1, event_name); - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } break; case 8: /* D1 page flip */ case 10: /* D2 page flip */ @@ -5264,162 +4784,45 @@ restart_ih: radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); break; case 42: /* HPD hotplug */ - switch (src_data) { - case 0: - if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD1\n"); - break; - case 1: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD2\n"); - break; - case 2: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD3\n"); - break; - case 3: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD4\n"); - break; - case 4: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD5\n"); - break; - case 5: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; + if (src_data <= 5) { + hpd_idx = src_data; + mask = DC_HPD1_INTERRUPT; queue_hotplug = true; - DRM_DEBUG("IH: HPD6\n"); - break; - case 6: - if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + event_name = "HPD"; - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; + } else if (src_data <= 11) { + hpd_idx = src_data - 6; + mask = DC_HPD1_RX_INTERRUPT; queue_dp = true; - DRM_DEBUG("IH: HPD_RX 1\n"); - break; - case 7: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + event_name = "HPD_RX"; - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 2\n"); - break; - case 8: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 3\n"); + } else { + DRM_DEBUG("Unhandled interrupt: %d %d\n", + src_id, src_data); break; - case 9: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + } - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 4\n"); - break; - case 10: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + if (!(disp_int[hpd_idx] & mask)) + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 5\n"); - break; - case 11: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + disp_int[hpd_idx] &= ~mask; + DRM_DEBUG("IH: %s%d\n", event_name, hpd_idx + 1); - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 6\n"); - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } break; case 44: /* hdmi */ - switch (src_data) { - case 0: - if (!(rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI0\n"); - break; - case 1: - if (!(rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI1\n"); - break; - case 2: - if (!(rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI2\n"); - break; - case 3: - if (!(rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + afmt_idx = src_data; + if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI3\n"); - break; - case 4: - if (!(rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI4\n"); - break; - case 5: - if (!(rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG; - queue_hdmi = true; - DRM_DEBUG("IH: HDMI5\n"); - break; - default: - DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); + if (afmt_idx > 5) { + DRM_ERROR("Unhandled interrupt: %d %d\n", + src_id, src_data); break; } + afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG; + queue_hdmi = true; + DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1); + break; case 96: DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); WREG32(SRBM_INT_ACK, 0x1); diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 342e3b1fb9c7..68be1bfa22b9 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -115,6 +115,8 @@ extern int radeon_auxch; extern int radeon_mst; extern int radeon_uvd; extern int radeon_vce; +extern int radeon_si_support; +extern int radeon_cik_support; /* * Copy from radeon_drv.h so we don't have to include both and have conflicting @@ -767,24 +769,9 @@ struct r600_irq_stat_regs { }; struct evergreen_irq_stat_regs { - u32 disp_int; - u32 disp_int_cont; - u32 disp_int_cont2; - u32 disp_int_cont3; - u32 disp_int_cont4; - u32 disp_int_cont5; - u32 d1grph_int; - u32 d2grph_int; - u32 d3grph_int; - u32 d4grph_int; - u32 d5grph_int; - u32 d6grph_int; - u32 afmt_status1; - u32 afmt_status2; - u32 afmt_status3; - u32 afmt_status4; - u32 afmt_status5; - u32 afmt_status6; + u32 disp_int[6]; + u32 grph_int[6]; + u32 afmt_status[6]; }; struct cik_irq_stat_regs { @@ -2976,6 +2963,12 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p, uint32_t *vline_start_end, uint32_t *vline_status); +/* interrupt control register helpers */ +void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, + u32 reg, u32 mask, + bool enable, const char *name, + unsigned n); + #include "radeon_object.h" #endif diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index 6f906abd612b..b23c771f4216 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -295,6 +295,14 @@ module_param_named(uvd, radeon_uvd, int, 0444); MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); module_param_named(vce, radeon_vce, int, 0444); +int radeon_si_support = 1; +MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); +module_param_named(si_support, radeon_si_support, int, 0444); + +int radeon_cik_support = 1; +MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); +module_param_named(cik_support, radeon_cik_support, int, 0444); + static struct pci_device_id pciidlist[] = { radeon_PCI_IDS }; diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index 1b7528df7f7f..7aacb44df201 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c +++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -538,3 +538,38 @@ void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask) spin_unlock_irqrestore(&rdev->irq.lock, irqflags); } +/** + * radeon_irq_kms_update_int_n - helper for updating interrupt enable registers + * + * @rdev: radeon device pointer + * @reg: the register to write to enable/disable interrupts + * @mask: the mask that enables the interrupts + * @enable: whether to enable or disable the interrupt register + * @name: the name of the interrupt register to print to the kernel log + * @num: the number of the interrupt register to print to the kernel log + * + * Helper for updating the enable state of interrupt registers. Checks whether + * or not the interrupt matches the enable state we want. If it doesn't, then + * we update it and print a debugging message to the kernel log indicating the + * new state of the interrupt register. + * + * Used for updating sequences of interrupts registers like HPD1, HPD2, etc. + */ +void radeon_irq_kms_set_irq_n_enabled(struct radeon_device *rdev, + u32 reg, u32 mask, + bool enable, const char *name, unsigned n) +{ + u32 tmp = RREG32(reg); + + /* Interrupt state didn't change */ + if (!!(tmp & mask) == enable) + return; + + if (enable) { + DRM_DEBUG("%s%d interrupts enabled\n", name, n); + WREG32(reg, tmp |= mask); + } else { + DRM_DEBUG("%s%d interrupts disabled\n", name, n); + WREG32(reg, tmp & ~mask); + } +} diff --git a/drivers/gpu/drm/radeon/radeon_kfd.c b/drivers/gpu/drm/radeon/radeon_kfd.c index 87a9ebb5f58f..699fe7f9b8bf 100644 --- a/drivers/gpu/drm/radeon/radeon_kfd.c +++ b/drivers/gpu/drm/radeon/radeon_kfd.c @@ -179,14 +179,29 @@ void radeon_kfd_device_probe(struct radeon_device *rdev) void radeon_kfd_device_init(struct radeon_device *rdev) { + int i, queue, pipe, mec; + if (rdev->kfd) { struct kgd2kfd_shared_resources gpu_resources = { .compute_vmid_bitmap = 0xFF00, - - .first_compute_pipe = 1, - .compute_pipe_count = 4 - 1, + .num_mec = 1, + .num_pipe_per_mec = 4, + .num_queue_per_pipe = 8 }; + bitmap_zero(gpu_resources.queue_bitmap, KGD_MAX_QUEUES); + + for (i = 0; i < KGD_MAX_QUEUES; ++i) { + queue = i % gpu_resources.num_queue_per_pipe; + pipe = (i / gpu_resources.num_queue_per_pipe) + % gpu_resources.num_pipe_per_mec; + mec = (i / gpu_resources.num_queue_per_pipe) + / gpu_resources.num_pipe_per_mec; + + if (mec == 0 && pipe > 0) + set_bit(i, gpu_resources.queue_bitmap); + } + radeon_doorbell_get_kfd_info(rdev, &gpu_resources.doorbell_physical_address, &gpu_resources.doorbell_aperture_size, @@ -423,18 +438,7 @@ static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, uint32_t hpd_size, uint64_t hpd_gpu_addr) { - uint32_t mec = (pipe_id / CIK_PIPE_PER_MEC) + 1; - uint32_t pipe = (pipe_id % CIK_PIPE_PER_MEC); - - lock_srbm(kgd, mec, pipe, 0, 0); - write_register(kgd, CP_HPD_EOP_BASE_ADDR, - lower_32_bits(hpd_gpu_addr >> 8)); - write_register(kgd, CP_HPD_EOP_BASE_ADDR_HI, - upper_32_bits(hpd_gpu_addr >> 8)); - write_register(kgd, CP_HPD_EOP_VMID, 0); - write_register(kgd, CP_HPD_EOP_CONTROL, hpd_size); - unlock_srbm(kgd); - + /* nothing to do here */ return 0; } diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index d0ad03674250..dfee8f7d94ae 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -98,6 +98,31 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) struct radeon_device *rdev; int r, acpi_status; + if (!radeon_si_support) { + switch (flags & RADEON_FAMILY_MASK) { + case CHIP_TAHITI: + case CHIP_PITCAIRN: + case CHIP_VERDE: + case CHIP_OLAND: + case CHIP_HAINAN: + dev_info(dev->dev, + "SI support disabled by module param\n"); + return -ENODEV; + } + } + if (!radeon_cik_support) { + switch (flags & RADEON_FAMILY_MASK) { + case CHIP_KAVERI: + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_KABINI: + case CHIP_MULLINS: + dev_info(dev->dev, + "CIK support disabled by module param\n"); + return -ENODEV; + } + } + rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); if (rdev == NULL) { return -ENOMEM; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 76d1888528e6..c88a80e1e3ad 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -139,6 +139,30 @@ static void si_fini_pg(struct radeon_device *rdev); static void si_fini_cg(struct radeon_device *rdev); static void si_rlc_stop(struct radeon_device *rdev); +static const u32 crtc_offsets[] = +{ + EVERGREEN_CRTC0_REGISTER_OFFSET, + EVERGREEN_CRTC1_REGISTER_OFFSET, + EVERGREEN_CRTC2_REGISTER_OFFSET, + EVERGREEN_CRTC3_REGISTER_OFFSET, + EVERGREEN_CRTC4_REGISTER_OFFSET, + EVERGREEN_CRTC5_REGISTER_OFFSET +}; + +static const u32 si_disp_int_status[] = +{ + DISP_INTERRUPT_STATUS, + DISP_INTERRUPT_STATUS_CONTINUE, + DISP_INTERRUPT_STATUS_CONTINUE2, + DISP_INTERRUPT_STATUS_CONTINUE3, + DISP_INTERRUPT_STATUS_CONTINUE4, + DISP_INTERRUPT_STATUS_CONTINUE5 +}; + +#define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc)) +#define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc)) +#define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc)) + static const u32 verde_rlc_save_restore_register_list[] = { (0x8000 << 16) | (0x98f4 >> 2), @@ -5916,6 +5940,7 @@ static void si_disable_interrupts(struct radeon_device *rdev) static void si_disable_interrupt_state(struct radeon_device *rdev) { + int i; u32 tmp; tmp = RREG32(CP_INT_CNTL_RING0) & @@ -5929,47 +5954,17 @@ static void si_disable_interrupt_state(struct radeon_device *rdev) WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); WREG32(GRBM_INT_CNTL, 0); WREG32(SRBM_INT_CNTL, 0); - if (rdev->num_crtc >= 2) { - WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 4) { - WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 6) { - WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); - WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); - } - - if (rdev->num_crtc >= 2) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 4) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); - } - if (rdev->num_crtc >= 6) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); - } + for (i = 0; i < rdev->num_crtc; i++) + WREG32(INT_MASK + crtc_offsets[i], 0); + for (i = 0; i < rdev->num_crtc; i++) + WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); if (!ASIC_IS_NODCE(rdev)) { WREG32(DAC_AUTODETECT_INT_CONTROL, 0); - tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD1_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD2_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD3_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD4_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD5_INT_CONTROL, tmp); - tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; - WREG32(DC_HPD6_INT_CONTROL, tmp); + for (i = 0; i < 6; i++) + WREG32_AND(DC_HPDx_INT_CONTROL(i), + DC_HPDx_INT_POLARITY); } } @@ -6044,12 +6039,12 @@ static int si_irq_init(struct radeon_device *rdev) return ret; } +/* The order we write back each register here is important */ int si_irq_set(struct radeon_device *rdev) { + int i; u32 cp_int_cntl; u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; - u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; - u32 hpd1 = 0, hpd2 = 0, hpd3 = 0, hpd4 = 0, hpd5 = 0, hpd6 = 0; u32 grbm_int_cntl = 0; u32 dma_cntl, dma_cntl1; u32 thermal_int = 0; @@ -6069,15 +6064,6 @@ int si_irq_set(struct radeon_device *rdev) cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); - if (!ASIC_IS_NODCE(rdev)) { - hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); - } - dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; @@ -6106,60 +6092,6 @@ int si_irq_set(struct radeon_device *rdev) DRM_DEBUG("si_irq_set: sw int dma1\n"); dma_cntl1 |= TRAP_ENABLE; } - if (rdev->irq.crtc_vblank_int[0] || - atomic_read(&rdev->irq.pflip[0])) { - DRM_DEBUG("si_irq_set: vblank 0\n"); - crtc1 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[1] || - atomic_read(&rdev->irq.pflip[1])) { - DRM_DEBUG("si_irq_set: vblank 1\n"); - crtc2 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[2] || - atomic_read(&rdev->irq.pflip[2])) { - DRM_DEBUG("si_irq_set: vblank 2\n"); - crtc3 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[3] || - atomic_read(&rdev->irq.pflip[3])) { - DRM_DEBUG("si_irq_set: vblank 3\n"); - crtc4 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[4] || - atomic_read(&rdev->irq.pflip[4])) { - DRM_DEBUG("si_irq_set: vblank 4\n"); - crtc5 |= VBLANK_INT_MASK; - } - if (rdev->irq.crtc_vblank_int[5] || - atomic_read(&rdev->irq.pflip[5])) { - DRM_DEBUG("si_irq_set: vblank 5\n"); - crtc6 |= VBLANK_INT_MASK; - } - if (rdev->irq.hpd[0]) { - DRM_DEBUG("si_irq_set: hpd 1\n"); - hpd1 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[1]) { - DRM_DEBUG("si_irq_set: hpd 2\n"); - hpd2 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[2]) { - DRM_DEBUG("si_irq_set: hpd 3\n"); - hpd3 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[3]) { - DRM_DEBUG("si_irq_set: hpd 4\n"); - hpd4 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[4]) { - DRM_DEBUG("si_irq_set: hpd 5\n"); - hpd5 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } - if (rdev->irq.hpd[5]) { - DRM_DEBUG("si_irq_set: hpd 6\n"); - hpd6 |= DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN; - } WREG32(CP_INT_CNTL_RING0, cp_int_cntl); WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); @@ -6175,45 +6107,23 @@ int si_irq_set(struct radeon_device *rdev) thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; } - if (rdev->num_crtc >= 2) { - WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); - WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); - } - if (rdev->num_crtc >= 4) { - WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); - WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); - } - if (rdev->num_crtc >= 6) { - WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); - WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); + for (i = 0; i < rdev->num_crtc; i++) { + radeon_irq_kms_set_irq_n_enabled( + rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, + rdev->irq.crtc_vblank_int[i] || + atomic_read(&rdev->irq.pflip[i]), "vblank", i); } - if (rdev->num_crtc >= 2) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - } - if (rdev->num_crtc >= 4) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - } - if (rdev->num_crtc >= 6) { - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, - GRPH_PFLIP_INT_MASK); - } + for (i = 0; i < rdev->num_crtc; i++) + WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); if (!ASIC_IS_NODCE(rdev)) { - WREG32(DC_HPD1_INT_CONTROL, hpd1); - WREG32(DC_HPD2_INT_CONTROL, hpd2); - WREG32(DC_HPD3_INT_CONTROL, hpd3); - WREG32(DC_HPD4_INT_CONTROL, hpd4); - WREG32(DC_HPD5_INT_CONTROL, hpd5); - WREG32(DC_HPD6_INT_CONTROL, hpd6); + for (i = 0; i < 6; i++) { + radeon_irq_kms_set_irq_n_enabled( + rdev, DC_HPDx_INT_CONTROL(i), + DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN, + rdev->irq.hpd[i], "HPD", i); + } } WREG32(CG_THERMAL_INT, thermal_int); @@ -6224,133 +6134,48 @@ int si_irq_set(struct radeon_device *rdev) return 0; } +/* The order we write back each register here is important */ static inline void si_irq_ack(struct radeon_device *rdev) { - u32 tmp; + int i, j; + u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; + u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; if (ASIC_IS_NODCE(rdev)) return; - rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); - rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); - rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); - rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); - rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); - rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); - rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); - if (rdev->num_crtc >= 4) { - rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); - } - if (rdev->num_crtc >= 6) { - rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); - rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); - } - - if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); - - if (rdev->num_crtc >= 4) { - if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); - } - - if (rdev->num_crtc >= 6) { - if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED) - WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) - WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) - WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); - } - - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) { - tmp = RREG32(DC_HPD1_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD1_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) { - tmp = RREG32(DC_HPD2_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD2_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) { - tmp = RREG32(DC_HPD3_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD3_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) { - tmp = RREG32(DC_HPD4_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD4_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) { - tmp = RREG32(DC_HPD5_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD5_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) { - tmp = RREG32(DC_HPD6_INT_CONTROL); - tmp |= DC_HPDx_INT_ACK; - WREG32(DC_HPD6_INT_CONTROL, tmp); - } - - if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT) { - tmp = RREG32(DC_HPD1_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD1_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT) { - tmp = RREG32(DC_HPD2_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD2_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) { - tmp = RREG32(DC_HPD3_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD3_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) { - tmp = RREG32(DC_HPD4_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD4_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) { - tmp = RREG32(DC_HPD5_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD5_INT_CONTROL, tmp); - } - if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) { - tmp = RREG32(DC_HPD6_INT_CONTROL); - tmp |= DC_HPDx_RX_INT_ACK; - WREG32(DC_HPD6_INT_CONTROL, tmp); + for (i = 0; i < 6; i++) { + disp_int[i] = RREG32(si_disp_int_status[i]); + if (i < rdev->num_crtc) + grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); + } + + /* We write back each interrupt register in pairs of two */ + for (i = 0; i < rdev->num_crtc; i += 2) { + for (j = i; j < (i + 2); j++) { + if (grph_int[j] & GRPH_PFLIP_INT_OCCURRED) + WREG32(GRPH_INT_STATUS + crtc_offsets[j], + GRPH_PFLIP_INT_CLEAR); + } + + for (j = i; j < (i + 2); j++) { + if (disp_int[j] & LB_D1_VBLANK_INTERRUPT) + WREG32(VBLANK_STATUS + crtc_offsets[j], + VBLANK_ACK); + if (disp_int[j] & LB_D1_VLINE_INTERRUPT) + WREG32(VLINE_STATUS + crtc_offsets[j], + VLINE_ACK); + } + } + + for (i = 0; i < 6; i++) { + if (disp_int[i] & DC_HPD1_INTERRUPT) + WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_INT_ACK); + } + + for (i = 0; i < 6; i++) { + if (disp_int[i] & DC_HPD1_RX_INTERRUPT) + WREG32_OR(DC_HPDx_INT_CONTROL(i), DC_HPDx_RX_INT_ACK); } } @@ -6412,6 +6237,9 @@ static inline u32 si_get_ih_wptr(struct radeon_device *rdev) */ int si_irq_process(struct radeon_device *rdev) { + u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; + u32 crtc_idx, hpd_idx; + u32 mask; u32 wptr; u32 rptr; u32 src_id, src_data, ring_id; @@ -6420,6 +6248,7 @@ int si_irq_process(struct radeon_device *rdev) bool queue_dp = false; bool queue_thermal = false; u32 status, addr; + const char *event_name; if (!rdev->ih.enabled || rdev->shutdown) return IRQ_NONE; @@ -6449,184 +6278,44 @@ restart_ih: switch (src_id) { case 1: /* D1 vblank/vline */ - switch (src_data) { - case 0: /* D1 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[0]) { - drm_handle_vblank(rdev->ddev, 0); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[0])) - radeon_crtc_handle_vblank(rdev, 0); - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D1 vblank\n"); - - break; - case 1: /* D1 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT; - DRM_DEBUG("IH: D1 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 2: /* D2 vblank/vline */ - switch (src_data) { - case 0: /* D2 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[1]) { - drm_handle_vblank(rdev->ddev, 1); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[1])) - radeon_crtc_handle_vblank(rdev, 1); - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D2 vblank\n"); - - break; - case 1: /* D2 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; - DRM_DEBUG("IH: D2 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 3: /* D3 vblank/vline */ - switch (src_data) { - case 0: /* D3 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[2]) { - drm_handle_vblank(rdev->ddev, 2); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[2])) - radeon_crtc_handle_vblank(rdev, 2); - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D3 vblank\n"); - - break; - case 1: /* D3 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; - DRM_DEBUG("IH: D3 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 4: /* D4 vblank/vline */ - switch (src_data) { - case 0: /* D4 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - if (rdev->irq.crtc_vblank_int[3]) { - drm_handle_vblank(rdev->ddev, 3); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[3])) - radeon_crtc_handle_vblank(rdev, 3); - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D4 vblank\n"); - - break; - case 1: /* D4 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; - DRM_DEBUG("IH: D4 vline\n"); - - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } - break; case 5: /* D5 vblank/vline */ - switch (src_data) { - case 0: /* D5 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + case 6: /* D6 vblank/vline */ + crtc_idx = src_id - 1; + + if (src_data == 0) { /* vblank */ + mask = LB_D1_VBLANK_INTERRUPT; + event_name = "vblank"; - if (rdev->irq.crtc_vblank_int[4]) { - drm_handle_vblank(rdev->ddev, 4); + if (rdev->irq.crtc_vblank_int[crtc_idx]) { + drm_handle_vblank(rdev->ddev, crtc_idx); rdev->pm.vblank_sync = true; wake_up(&rdev->irq.vblank_queue); } - if (atomic_read(&rdev->irq.pflip[4])) - radeon_crtc_handle_vblank(rdev, 4); - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D5 vblank\n"); - - break; - case 1: /* D5 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; - DRM_DEBUG("IH: D5 vline\n"); + if (atomic_read(&rdev->irq.pflip[crtc_idx])) { + radeon_crtc_handle_vblank(rdev, + crtc_idx); + } - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); + } else if (src_data == 1) { /* vline */ + mask = LB_D1_VLINE_INTERRUPT; + event_name = "vline"; + } else { + DRM_DEBUG("Unhandled interrupt: %d %d\n", + src_id, src_data); break; } - break; - case 6: /* D6 vblank/vline */ - switch (src_data) { - case 0: /* D6 vblank */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - if (rdev->irq.crtc_vblank_int[5]) { - drm_handle_vblank(rdev->ddev, 5); - rdev->pm.vblank_sync = true; - wake_up(&rdev->irq.vblank_queue); - } - if (atomic_read(&rdev->irq.pflip[5])) - radeon_crtc_handle_vblank(rdev, 5); - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; - DRM_DEBUG("IH: D6 vblank\n"); - - break; - case 1: /* D6 vline */ - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + if (!(disp_int[crtc_idx] & mask)) { + DRM_DEBUG("IH: D%d %s - IH event w/o asserted irq bit?\n", + crtc_idx + 1, event_name); + } - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; - DRM_DEBUG("IH: D6 vline\n"); + disp_int[crtc_idx] &= ~mask; + DRM_DEBUG("IH: D%d %s\n", crtc_idx + 1, event_name); - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } break; case 8: /* D1 page flip */ case 10: /* D2 page flip */ @@ -6639,119 +6328,29 @@ restart_ih: radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); break; case 42: /* HPD hotplug */ - switch (src_data) { - case 0: - if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD1\n"); - - break; - case 1: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT; + if (src_data <= 5) { + hpd_idx = src_data; + mask = DC_HPD1_INTERRUPT; queue_hotplug = true; - DRM_DEBUG("IH: HPD2\n"); + event_name = "HPD"; - break; - case 2: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD3\n"); - - break; - case 3: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD4\n"); - - break; - case 4: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD5\n"); - - break; - case 5: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT; - queue_hotplug = true; - DRM_DEBUG("IH: HPD6\n"); - - break; - case 6: - if (!(rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_RX_INTERRUPT; + } else if (src_data <= 11) { + hpd_idx = src_data - 6; + mask = DC_HPD1_RX_INTERRUPT; queue_dp = true; - DRM_DEBUG("IH: HPD_RX 1\n"); - - break; - case 7: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 2\n"); - - break; - case 8: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 3\n"); - - break; - case 9: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 4\n"); - - break; - case 10: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - - rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 5\n"); + event_name = "HPD_RX"; + } else { + DRM_DEBUG("Unhandled interrupt: %d %d\n", + src_id, src_data); break; - case 11: - if (!(rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_RX_INTERRUPT)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + } - rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT; - queue_dp = true; - DRM_DEBUG("IH: HPD_RX 6\n"); + if (!(disp_int[hpd_idx] & mask)) + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - break; - default: - DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); - break; - } + disp_int[hpd_idx] &= ~mask; + DRM_DEBUG("IH: %s%d\n", event_name, hpd_idx + 1); break; case 96: DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); |