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| author | Thierry Reding <treding@nvidia.com> | 2015-07-21 16:33:48 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-28 11:18:44 +0100 |
| commit | c728e2d4a6546905f1179a8237860d8d276aaadc (patch) | |
| tree | f2d9a04f94615a5a73cc84f1371eeecf709675b2 /drivers/gpu/drm/tegra/dpaux.c | |
| parent | drm/tegra: dp: Add drm_dp_link_reset() implementation (diff) | |
| download | linux-c728e2d4a6546905f1179a8237860d8d276aaadc.tar.xz linux-c728e2d4a6546905f1179a8237860d8d276aaadc.zip | |
drm/tegra: dp: Track link capabilities alongside settings
Store capabilities in max_* fields and add separate fields for the
currently selected settings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/dpaux.c')
| -rw-r--r-- | drivers/gpu/drm/tegra/dpaux.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index 883ed2f025c3..bd3361cea49b 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -849,14 +849,14 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, if (tp == DP_TRAINING_PATTERN_DISABLE) return 0; - for (i = 0; i < link->num_lanes; i++) + for (i = 0; i < link->lanes; i++) values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | DP_TRAIN_PRE_EMPH_LEVEL_0 | DP_TRAIN_MAX_SWING_REACHED | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; err = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, values, - link->num_lanes); + link->lanes); if (err < 0) return err; @@ -868,13 +868,13 @@ int drm_dp_aux_train(struct drm_dp_aux *aux, struct drm_dp_link *link, switch (tp) { case DP_TRAINING_PATTERN_1: - if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) + if (!drm_dp_clock_recovery_ok(status, link->lanes)) return -EAGAIN; break; case DP_TRAINING_PATTERN_2: - if (!drm_dp_channel_eq_ok(status, link->num_lanes)) + if (!drm_dp_channel_eq_ok(status, link->lanes)) return -EAGAIN; break; |