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author | Thierry Reding <treding@nvidia.com> | 2015-01-19 16:15:04 +0100 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2015-06-12 16:23:50 +0200 |
commit | 4553f733c68b66ef49f838aa24470d58caf76ff5 (patch) | |
tree | d6d170f2bdc1d0fa3f6f8f539effadb837423241 /drivers/gpu/drm/tegra | |
parent | drm/tegra: dpaux: Fix transfers larger than 4 bytes (diff) | |
download | linux-4553f733c68b66ef49f838aa24470d58caf76ff5.tar.xz linux-4553f733c68b66ef49f838aa24470d58caf76ff5.zip |
drm/tegra: gem: Take into account IOMMU aperture
The IOMMU may not always be able to address 2 GiB of memory. On Tegra20,
the GART supports 32 MiB starting at 0x58000000. Also the aperture on
Tegra30 and later is in fact the full 4 GiB, rather than just 2 GiB as
currently assumed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
-rw-r--r-- | drivers/gpu/drm/tegra/drm.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 1833abd7d3aa..106208463b37 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -124,14 +124,22 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) return -ENOMEM; if (iommu_present(&platform_bus_type)) { + struct iommu_domain_geometry *geometry; + u64 start, end; + tegra->domain = iommu_domain_alloc(&platform_bus_type); if (!tegra->domain) { err = -ENOMEM; goto free; } - DRM_DEBUG("IOMMU context initialized\n"); - drm_mm_init(&tegra->mm, 0, SZ_2G); + geometry = &tegra->domain->geometry; + start = geometry->aperture_start; + end = geometry->aperture_end; + + DRM_DEBUG("IOMMU context initialized (aperture: %#llx-%#llx)\n", + start, end); + drm_mm_init(&tegra->mm, start, end - start + 1); } mutex_init(&tegra->clients_lock); |