diff options
| author | Tomeu Vizoso <tomeu.vizoso@collabora.com> | 2015-03-30 10:33:03 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2015-04-02 18:49:24 +0200 |
| commit | 535a65db484ff4e4654a037f2ea7e1ff21431b77 (patch) | |
| tree | 5dcab872d151dbd0c89208e96022c6ea3e7396cc /drivers/gpu/drm/tegra | |
| parent | drm/tegra: gem: Return 64-bit offset for mmap(2) (diff) | |
| download | linux-535a65db484ff4e4654a037f2ea7e1ff21431b77.tar.xz linux-535a65db484ff4e4654a037f2ea7e1ff21431b77.zip | |
drm/tegra: sor: Reset during initialization
As there isn't a way for the firmware on the Nyan Chromebooks to hand
over the display to the kernel, and the kernel isn't redoing the whole
configuration at present.
With this patch, the SOR is brought to a known state and we get correct
display on every boot.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra')
| -rw-r--r-- | drivers/gpu/drm/tegra/sor.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 41c5a6ed2c36..7591d8901f9a 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -1512,12 +1512,30 @@ static int tegra_sor_init(struct host1x_client *client) } } + /* + * XXX: Remove this reset once proper hand-over from firmware to + * kernel is possible. + */ + err = reset_control_assert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to assert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk); if (err < 0) { dev_err(sor->dev, "failed to enable clock: %d\n", err); return err; } + usleep_range(1000, 3000); + + err = reset_control_deassert(sor->rst); + if (err < 0) { + dev_err(sor->dev, "failed to deassert SOR reset: %d\n", err); + return err; + } + err = clk_prepare_enable(sor->clk_safe); if (err < 0) return err; |