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| author | Michel Dänzer <daenzer@vmware.com> | 2009-06-15 16:56:13 +0200 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-06-19 01:24:53 +0200 |
| commit | 46f4b3eab73e621bc239bfa62ebdc44dcc0a877a (patch) | |
| tree | 242528337269c59a967560b7141b87ff33150db9 /drivers/gpu/drm | |
| parent | radeon: Enable modesetting on non-x86. (diff) | |
| download | linux-46f4b3eab73e621bc239bfa62ebdc44dcc0a877a.tar.xz linux-46f4b3eab73e621bc239bfa62ebdc44dcc0a877a.zip | |
drm/ttm: Add some powerpc cache flush code.
Optimise the powerpc flushing path for TTM.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/ttm/ttm_tt.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index c27ab3a877ad..0331fa74cd3f 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -68,7 +68,7 @@ static void ttm_tt_cache_flush_clflush(struct page *pages[], ttm_tt_clflush_page(*pages++); mb(); } -#else +#elif !defined(__powerpc__) static void ttm_tt_ipi_handler(void *null) { ; @@ -83,6 +83,15 @@ void ttm_tt_cache_flush(struct page *pages[], unsigned long num_pages) ttm_tt_cache_flush_clflush(pages, num_pages); return; } +#elif defined(__powerpc__) + unsigned long i; + + for (i = 0; i < num_pages; ++i) { + if (pages[i]) { + unsigned long start = (unsigned long)page_address(pages[i]); + flush_dcache_range(start, start + PAGE_SIZE); + } + } #else if (on_each_cpu(ttm_tt_ipi_handler, NULL, 1) != 0) printk(KERN_ERR TTM_PFX |