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authorAlex Deucher <alexander.deucher@amd.com>2019-07-24 06:27:21 +0200
committerAlex Deucher <alexander.deucher@amd.com>2019-07-31 06:23:44 +0200
commit0cf3c64f294c1a03e7e1d826c6c9d1b126216c02 (patch)
treee4effb7fa158a35d2d6221f3a0ff97fe20e35e93 /drivers/gpu/drm
parentdrm/amd/powerplay: enable SW SMU reset functionality (diff)
downloadlinux-0cf3c64f294c1a03e7e1d826c6c9d1b126216c02.tar.xz
linux-0cf3c64f294c1a03e7e1d826c6c9d1b126216c02.zip
drm/amdgpu: add an asic callback to determine the reset method
Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ca8b325291a3..5cbed256f006 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -532,6 +532,14 @@ struct amdgpu_allowed_register_entry {
bool grbm_indexed;
};
+enum amd_reset_method {
+ AMD_RESET_METHOD_LEGACY = 0,
+ AMD_RESET_METHOD_MODE0,
+ AMD_RESET_METHOD_MODE1,
+ AMD_RESET_METHOD_MODE2,
+ AMD_RESET_METHOD_BACO
+};
+
/*
* ASIC specific functions.
*/
@@ -543,6 +551,7 @@ struct amdgpu_asic_funcs {
u32 sh_num, u32 reg_offset, u32 *value);
void (*set_vga_state)(struct amdgpu_device *adev, bool state);
int (*reset)(struct amdgpu_device *adev);
+ enum amd_reset_method (*reset_method)(struct amdgpu_device *adev);
/* get the reference clock */
u32 (*get_xclk)(struct amdgpu_device *adev);
/* MM block clocks */
@@ -1109,6 +1118,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
*/
#define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
#define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
+#define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev))
#define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
#define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
#define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))