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authorThierry Reding <thierry.reding@avionic-design.de>2013-04-22 21:31:15 +0200
committerThierry Reding <thierry.reding@gmail.com>2013-05-25 12:32:50 +0200
commited683aead1962f2242c8dc8863517bcd3089703d (patch)
treea6a194a75a9f12d4c2ac6889b7283f39aa118327 /drivers/gpu/host1x/drm/dc.c
parentdrm/tegra: Explicitly set irq_enabled (diff)
downloadlinux-ed683aead1962f2242c8dc8863517bcd3089703d.tar.xz
linux-ed683aead1962f2242c8dc8863517bcd3089703d.zip
drm/tegra: Honor pixel-format changes
When using a base mode-set, honor changes in pixel-format since the core doesn't explicitly check for them as long as they use the same depth. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Diffstat (limited to 'drivers/gpu/host1x/drm/dc.c')
-rw-r--r--drivers/gpu/host1x/drm/dc.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/host1x/drm/dc.c b/drivers/gpu/host1x/drm/dc.c
index 98f60d827558..5360e5a57ecc 100644
--- a/drivers/gpu/host1x/drm/dc.c
+++ b/drivers/gpu/host1x/drm/dc.c
@@ -143,6 +143,7 @@ static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
struct drm_framebuffer *fb)
{
+ unsigned int format = tegra_dc_format(fb->pixel_format);
struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
unsigned long value;
@@ -153,6 +154,7 @@ static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
+ tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
value = GENERAL_UPDATE | WIN_A_UPDATE;
tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);