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| author | Thierry Reding <treding@nvidia.com> | 2019-02-01 14:28:28 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-02-07 18:28:58 +0100 |
| commit | 8de896eb206fea3caa26b5fc8e637934d8486f0f (patch) | |
| tree | aa91a837906c7d044aeb4b9ff493ac57aaca51ff /drivers/gpu/host1x | |
| parent | gpu: host1x: Restrict IOVA space to DMA mask (diff) | |
| download | linux-8de896eb206fea3caa26b5fc8e637934d8486f0f.tar.xz linux-8de896eb206fea3caa26b5fc8e637934d8486f0f.zip | |
gpu: host1x: Support 40-bit addressing on Tegra186
The host1x and clients instantiated on Tegra186 support addressing 40
bits of memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/host1x')
| -rw-r--r-- | drivers/gpu/host1x/dev.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c index 544b67f2b3ff..ee3c7b81a29d 100644 --- a/drivers/gpu/host1x/dev.c +++ b/drivers/gpu/host1x/dev.c @@ -136,7 +136,7 @@ static const struct host1x_info host1x06_info = { .nb_bases = 16, .init = host1x06_init, .sync_offset = 0x0, - .dma_mask = DMA_BIT_MASK(34), + .dma_mask = DMA_BIT_MASK(40), .has_hypervisor = true, .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), .sid_table = tegra186_sid_table, |