diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2017-04-17 23:30:27 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-05-02 19:15:39 +0200 |
| commit | 0274a9c55614a5c89dd04bca376dbe252f5ea334 (patch) | |
| tree | 7fcba10ab39c435f2b9ccb5671da13ba3e0c1d6c /drivers/gpu | |
| parent | drm/amdgpu/gfx9: use actual gpu num se setting for ngg allocation (diff) | |
| download | linux-0274a9c55614a5c89dd04bca376dbe252f5ea334.tar.xz linux-0274a9c55614a5c89dd04bca376dbe252f5ea334.zip | |
drm/amdgpu/gfx9: fix typo in mpd init
Using the wrong macro for soc15 register access.
Reviewed-by: monk liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ad2e08a943cd..178fe11bd7f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1989,12 +1989,12 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring) /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ ring->wptr = 0; - mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR); + mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); /* set the vmid for the queue */ mqd->cp_hqd_vmid = 0; - tmp = RREG32(mmCP_HQD_PERSISTENT_STATE); + tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); mqd->cp_hqd_persistent_state = tmp; |