diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-08-19 03:46:15 +0200 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-22 08:28:54 +0200 |
| commit | 3fdef0205e69b80c4219f14b834cb85eb719039f (patch) | |
| tree | 31f0fc0b6d48661bec5f165971b311a3521a8846 /drivers/gpu | |
| parent | agp/intel: set 40-bit dma mask on Sandybridge (diff) | |
| download | linux-3fdef0205e69b80c4219f14b834cb85eb719039f.tar.xz linux-3fdef0205e69b80c4219f14b834cb85eb719039f.zip | |
drm/i915: fix render pipe control notify on sandybridge
This one is missed in last pipe control fix for sandybridge,
that really unmask interrupt bit for notify in render engine IMR.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 69a36fc035dc..16861b800fee 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1381,12 +1381,17 @@ static int ironlake_irq_postinstall(struct drm_device *dev) I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); (void) I915_READ(DEIER); - /* user interrupt should be enabled, but masked initial */ + /* Gen6 only needs render pipe_control now */ + if (IS_GEN6(dev)) + render_mask = GT_PIPE_NOTIFY; + dev_priv->gt_irq_mask_reg = ~render_mask; dev_priv->gt_irq_enable_reg = render_mask; I915_WRITE(GTIIR, I915_READ(GTIIR)); I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); + if (IS_GEN6(dev)) + I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); (void) I915_READ(GTIER); |