diff options
| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-02-14 14:44:48 +0100 |
|---|---|---|
| committer | Jesse Barnes <jbarnes@virtuousgeek.org> | 2012-02-16 02:43:41 +0100 |
| commit | 1c8ecf80fdee4e7b23a9e7da7ff9bd59ba2dcf96 (patch) | |
| tree | 0cbb7a8b88c100acb3df605fc8908845729765cb /drivers/gpu | |
| parent | drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs. (diff) | |
| download | linux-1c8ecf80fdee4e7b23a9e7da7ff9bd59ba2dcf96.tar.xz linux-1c8ecf80fdee4e7b23a9e7da7ff9bd59ba2dcf96.zip | |
drm/i915: do not enable RC6p on Sandy Bridge
With base on latest findings, RC6p seems to be respondible for RC6-related
issues on Sandy Bridge platform. To work-around those issues, the previous
solution was to completely disable RC6 on Sandy Bridge for the past few
releases, even if plain RC6 was not giving any issues.
What this patch does is preventing RC6p from being enabled on Sandy Bridge
even if users enable RC6 via a kernel parameter. So it won't change the
defaults in any way, but will ensure that if users do enable RC6 manually
it won't break their machines by enabling this extra state.
Proper fix for this (enabling specific RC6 states according to the GPU
generation) were proposed for the -next kernel, but we are too late in the
release process now to pick such changes.
Acked-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d9b042b1d14d..049804eee290 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8182,8 +8182,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ if (intel_enable_rc6(dev_priv->dev)) - rc6_mask = GEN6_RC_CTL_RC6p_ENABLE | - GEN6_RC_CTL_RC6_ENABLE; + rc6_mask = GEN6_RC_CTL_RC6_ENABLE | + (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0; I915_WRITE(GEN6_RC_CONTROL, rc6_mask | |