diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-03-12 00:28:39 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-03-15 23:47:17 +0100 |
| commit | 8f612b23a17dce86fef75407e698de6243cc99a1 (patch) | |
| tree | de94464a0baae97de4d142324d990f8f4f5424ea /drivers/gpu | |
| parent | drm/radeon: fix S/R on VM systems (cayman/TN/SI) (diff) | |
| download | linux-8f612b23a17dce86fef75407e698de6243cc99a1.tar.xz linux-8f612b23a17dce86fef75407e698de6243cc99a1.zip | |
drm/radeon: fix backend map setup on 1 RB trinity boards
Need to adjust the backend map depending on which RB is
enabled. This is the trinity equivalent of:
f7eb97300832f4fe5fe916c5d84cd2e25169330e
May fix:
https://bugs.freedesktop.org/show_bug.cgi?id=57919
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index e77c9273bc9c..a7d3de73be04 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c @@ -616,11 +616,22 @@ static void cayman_gpu_init(struct radeon_device *rdev) WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); - tmp = gb_addr_config & NUM_PIPES_MASK; - tmp = r6xx_remap_render_backend(rdev, tmp, - rdev->config.cayman.max_backends_per_se * - rdev->config.cayman.max_shader_engines, - CAYMAN_MAX_BACKENDS, disabled_rb_mask); + if ((rdev->config.cayman.max_backends_per_se == 1) && + (rdev->flags & RADEON_IS_IGP)) { + if ((disabled_rb_mask & 3) == 1) { + /* RB0 disabled, RB1 enabled */ + tmp = 0x11111111; + } else { + /* RB1 disabled, RB0 enabled */ + tmp = 0x00000000; + } + } else { + tmp = gb_addr_config & NUM_PIPES_MASK; + tmp = r6xx_remap_render_backend(rdev, tmp, + rdev->config.cayman.max_backends_per_se * + rdev->config.cayman.max_shader_engines, + CAYMAN_MAX_BACKENDS, disabled_rb_mask); + } WREG32(GB_BACKEND_MAP, tmp); cgts_tcc_disable = 0xffff0000; |