diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> | 2021-01-09 14:51:11 +0100 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2021-02-01 17:53:25 +0100 |
| commit | 362cadf34b9fe030f271ded38d5062eac12f3340 (patch) | |
| tree | ff599cb0c5b7968b6056817d55833d6799f49924 /drivers/gpu | |
| parent | drm/msm/dsi_pll_10nm: Solve TODO for multiplier frac_bits assignment (diff) | |
| download | linux-362cadf34b9fe030f271ded38d5062eac12f3340.tar.xz linux-362cadf34b9fe030f271ded38d5062eac12f3340.zip | |
drm/msm/dsi_pll_10nm: Fix variable usage for pll_lockdet_rate
The PLL_LOCKDET_RATE_1 was being programmed with a hardcoded value
directly, but the same value was also being specified in the
dsi_pll_regs struct pll_lockdet_rate variable: let's use it!
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 72306a86c41f..2e1cb4154c0f 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -304,7 +304,8 @@ static void dsi_pll_commit(struct dsi_pll_10nm *pll) reg->frac_div_start_mid); pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1, reg->frac_div_start_high); - pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40); + pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, + reg->pll_lockdet_rate); pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06); pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10); pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS, |