diff options
| author | Manasi Navare <manasi.d.navare@intel.com> | 2018-06-12 00:26:54 +0200 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2018-06-14 23:57:01 +0200 |
| commit | 46b527d19c4327897197d09748a8b332e322a1d7 (patch) | |
| tree | d542151a07870c6a10da142f8a8d079a9bb48b66 /drivers/gpu | |
| parent | drm/i915/icl: start adding the TBT pll (diff) | |
| download | linux-46b527d19c4327897197d09748a8b332e322a1d7.tar.xz linux-46b527d19c4327897197d09748a8b332e322a1d7.zip | |
drm/i915/icl: Add allowed DP rates for Icelake
For ICL, on Combo PHY the allowed max rates are:
- HBR3 8.1 eDP (DDIA)
- HBR2 5.4 DisplayPort (DDIB)
and for MG PHY/TC DDI Ports allowed DP rates are:
- HBR3 8.1 DisplayPort (DP alternate mode, DP over TBT,
- DP on legacy connector - DDIC/D/E/F)
v2 (from Paulo): Remove misleading comment (Ville).
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
[Paulo: bikeshed to keep future platforms on "else", v2.]
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180611222655.5696-1-paulo.r.zanoni@intel.com
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 67875b00c8df..af5314229ffe 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -256,6 +256,17 @@ static int cnl_max_source_rate(struct intel_dp *intel_dp) return 810000; } +static int icl_max_source_rate(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + enum port port = dig_port->base.port; + + if (port == PORT_B) + return 540000; + + return 810000; +} + static void intel_dp_set_source_rates(struct intel_dp *intel_dp) { @@ -285,10 +296,13 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); - if (IS_CANNONLAKE(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 10) { source_rates = cnl_rates; size = ARRAY_SIZE(cnl_rates); - max_rate = cnl_max_source_rate(intel_dp); + if (INTEL_GEN(dev_priv) == 10) + max_rate = cnl_max_source_rate(intel_dp); + else + max_rate = icl_max_source_rate(intel_dp); } else if (IS_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); |