diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2012-03-20 22:18:34 +0100 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2012-03-21 07:55:56 +0100 |
| commit | 0671bdd7983c4df674cd0fce263a44cd87bd36d2 (patch) | |
| tree | 76a05f91d8c6c6a0a9c9acaf66e8bb1356d8a237 /drivers/gpu | |
| parent | drm/radeon/kms: disable PPLL0 on DCE6.1 when not in use (diff) | |
| download | linux-0671bdd7983c4df674cd0fce263a44cd87bd36d2.tar.xz linux-0671bdd7983c4df674cd0fce263a44cd87bd36d2.zip | |
drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls
It's handled via external clock. It should already be protected
by the external ss flag, but add an explicit check just in case.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index a5c4e3fa6bb2..083b3eada001 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -474,7 +474,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev, return; } args.v3.ucEnable = enable; - if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) + if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev)) args.v3.ucEnable = ATOM_DISABLE; } else if (ASIC_IS_DCE4(rdev)) { args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); |