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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-09-19 22:00:37 +0200 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-10-03 20:01:27 +0200 |
commit | dda9a66a818d32cbf5c4ecd817456fb6a3b39ec1 (patch) | |
tree | 14af313966e082e276ebdac25b040b8e6bf8a52b /drivers/hv | |
parent | i915/vlv: untangle integrated clock source handling v4 (diff) | |
download | linux-dda9a66a818d32cbf5c4ecd817456fb6a3b39ec1.tar.xz linux-dda9a66a818d32cbf5c4ecd817456fb6a3b39ec1.zip |
drm/i915: Disable/enable planes as the first/last thing during modeset on HSW
Refactor the plane enabling/disabling into helper functions and move
the calls to happen as the first thing during .crtc_disable, and the
last thing during .crtc_enable.
Those are the two clear points where we are sure that the pipe is
actually running regardless of the encoder type or hardware
generation.
v2: Made by Paulo:
Remove the code touching everything but the Haswell functions. We
need this change on Haswell right now since it fixes a FIFO underrun
that we get on pipe A while we enable pipe B (see the workaround
notes on the Haswell mode set sequence documentation). We can bring
back the code to gens 2-7 later, once they're tested.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/hv')
0 files changed, 0 insertions, 0 deletions