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authorAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>2020-07-01 09:22:33 +0200
committerMichael Ellerman <mpe@ellerman.id.au>2020-07-16 05:00:23 +0200
commit76e6c73f33d4e1cc4de4f25c0bf66d59e42113c4 (patch)
treec76d88ed281803424e6ed5b2635874209af25889 /drivers/hwmon/nct7802.c
parentlibnvdimm/nvdimm/flush: Allow architecture to override the flush barrier (diff)
downloadlinux-76e6c73f33d4e1cc4de4f25c0bf66d59e42113c4.tar.xz
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powerpc/pmem: Update ppc64 to use the new barrier instruction.
pmem on POWER10 can now use phwsync instead of hwsync to ensure all previous writes are architecturally visible for the platform buffer flush. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200701072235.223558-6-aneesh.kumar@linux.ibm.com
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