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| author | Heiner Kallweit <hkallweit1@gmail.com> | 2022-12-19 19:16:08 +0100 |
|---|---|---|
| committer | Wolfram Sang <wsa@kernel.org> | 2023-02-12 22:10:53 +0100 |
| commit | eb4d8bac03bc20c5f2975da325e2d669882ef03e (patch) | |
| tree | bb9412073eb92941575453a916bf5bcf9f0d038f /drivers/i2c | |
| parent | i2c: i801: make FEATURE_BLOCK_PROC dependent on FEATURE_BLOCK_BUFFER (diff) | |
| download | linux-eb4d8bac03bc20c5f2975da325e2d669882ef03e.tar.xz linux-eb4d8bac03bc20c5f2975da325e2d669882ef03e.zip | |
i2c: i801: add helper i801_set_hstadd()
Factor out setting SMBHSTADD to a helper. The current code makes the
assumption that constant I2C_SMBUS_READ has bit 0 set, that's not ideal.
Therefore let the new helper explicitly check for I2C_SMBUS_READ.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/busses/i2c-i801.c | 36 |
1 files changed, 16 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 2e9c5856a29f..882cf5135403 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -727,6 +727,11 @@ exit: return i801_check_post(priv, status); } +static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) +{ + outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); +} + /* Block transaction function */ static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, char read_write, int command) @@ -797,28 +802,24 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, switch (size) { case I2C_SMBUS_QUICK: - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, read_write); xact = I801_QUICK; break; case I2C_SMBUS_BYTE: - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, read_write); if (read_write == I2C_SMBUS_WRITE) outb_p(command, SMBHSTCMD(priv)); xact = I801_BYTE; break; case I2C_SMBUS_BYTE_DATA: - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, read_write); outb_p(command, SMBHSTCMD(priv)); if (read_write == I2C_SMBUS_WRITE) outb_p(data->byte, SMBHSTDAT0(priv)); xact = I801_BYTE_DATA; break; case I2C_SMBUS_WORD_DATA: - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, read_write); outb_p(command, SMBHSTCMD(priv)); if (read_write == I2C_SMBUS_WRITE) { outb_p(data->word & 0xff, SMBHSTDAT0(priv)); @@ -827,7 +828,7 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, xact = I801_WORD_DATA; break; case I2C_SMBUS_PROC_CALL: - outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); outb_p(command, SMBHSTCMD(priv)); outb_p(data->word & 0xff, SMBHSTDAT0(priv)); outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); @@ -835,8 +836,7 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, read_write = I2C_SMBUS_READ; break; case I2C_SMBUS_BLOCK_DATA: - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, read_write); outb_p(command, SMBHSTCMD(priv)); block = 1; break; @@ -847,10 +847,9 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, * However if SPD Write Disable is set (Lynx Point and later), * the read will fail if we don't set the R/#W bit. */ - outb_p(((addr & 0x7f) << 1) | - ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? - (read_write & 0x01) : 0), - SMBHSTADD(priv)); + i801_set_hstadd(priv, addr, + priv->original_hstcfg & SMBHSTCFG_SPD_WD ? + read_write : I2C_SMBUS_WRITE); if (read_write == I2C_SMBUS_READ) { /* NB: page 240 of ICH5 datasheet also shows * that DATA1 is the cmd field when reading */ @@ -860,11 +859,8 @@ static s32 i801_access(struct i2c_adapter *adap, u16 addr, block = 1; break; case I2C_SMBUS_BLOCK_PROC_CALL: - /* - * Bit 0 of the slave address register always indicate a write - * command. - */ - outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); + /* Needs to be flagged as write transaction */ + i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); outb_p(command, SMBHSTCMD(priv)); block = 1; break; |