diff options
| author | Abhilash Kesavan <a.kesavan@samsung.com> | 2014-11-01 05:00:43 +0100 |
|---|---|---|
| committer | Jonathan Cameron <jic23@kernel.org> | 2014-11-05 16:38:25 +0100 |
| commit | c1b501564c98a94b48f4ed936737403108dc7300 (patch) | |
| tree | f099f3c59337f23e1012954e5187b00d86d35a84 /drivers/iio | |
| parent | ARM: dts: exynos: Add sysreg phandle to ADC node (diff) | |
| download | linux-c1b501564c98a94b48f4ed936737403108dc7300.tar.xz linux-c1b501564c98a94b48f4ed936737403108dc7300.zip | |
iio: adc: exynos_adc: Add support for exynos7
The ADC on exynos7 is quite similar to ADCv2. The differences are as
follows:
- exynos7-adc has 8 input channels (as against 10 in ADCv2).
- exynos7 does not include an ADC PHY control register.
- Some ADC_CON2 register bits being used in ADCv2 are listed as
reserved in exynos7-adc. This results in a different init_hw
function for exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers/iio')
| -rw-r--r-- | drivers/iio/adc/exynos_adc.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index fe0317745436..3a2dbb3b4926 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -390,6 +390,35 @@ static const struct exynos_adc_data exynos3250_adc_data = { .start_conv = exynos_adc_v2_start_conv, }; +static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) +{ + u32 con1, con2; + + if (info->data->needs_adc_phy) + regmap_write(info->pmu_map, info->data->phy_offset, 1); + + con1 = ADC_V2_CON1_SOFT_RESET; + writel(con1, ADC_V2_CON1(info->regs)); + + con2 = readl(ADC_V2_CON2(info->regs)); + con2 &= ~ADC_V2_CON2_C_TIME(7); + con2 |= ADC_V2_CON2_C_TIME(0); + writel(con2, ADC_V2_CON2(info->regs)); + + /* Enable interrupts */ + writel(1, ADC_V2_INT_EN(info->regs)); +} + +static const struct exynos_adc_data exynos7_adc_data = { + .num_channels = MAX_ADC_V1_CHANNELS, + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ + + .init_hw = exynos_adc_exynos7_init_hw, + .exit_hw = exynos_adc_v2_exit_hw, + .clear_irq = exynos_adc_v2_clear_irq, + .start_conv = exynos_adc_v2_start_conv, +}; + static const struct of_device_id exynos_adc_match[] = { { .compatible = "samsung,s3c2410-adc", @@ -415,6 +444,9 @@ static const struct of_device_id exynos_adc_match[] = { }, { .compatible = "samsung,exynos3250-adc", .data = &exynos3250_adc_data, + }, { + .compatible = "samsung,exynos7-adc", + .data = &exynos7_adc_data, }, {}, }; |