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authorDavid S. Miller <davem@davemloft.net>2018-09-18 18:33:27 +0200
committerDavid S. Miller <davem@davemloft.net>2018-09-18 18:33:27 +0200
commite366fa435032db1ce1538a2c029714666985dd48 (patch)
treed08bab02ba212339e4cfc0f2e3666435dd795b90 /drivers/infiniband
parentnet: mdio: remove duplicated include from mdio_bus.c (diff)
parentMerge gitolite.kernel.org:/pub/scm/linux/kernel/git/davem/net (diff)
downloadlinux-e366fa435032db1ce1538a2c029714666985dd48.tar.xz
linux-e366fa435032db1ce1538a2c029714666985dd48.zip
Merge ra.kernel.org:/pub/scm/linux/kernel/git/davem/net
Two new tls tests added in parallel in both net and net-next. Used Stephen Rothwell's linux-next resolution. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/infiniband')
-rw-r--r--drivers/infiniband/hw/hfi1/pcie.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c
index eec83757d55f..6c967dde58e7 100644
--- a/drivers/infiniband/hw/hfi1/pcie.c
+++ b/drivers/infiniband/hw/hfi1/pcie.c
@@ -893,14 +893,11 @@ static int trigger_sbr(struct hfi1_devdata *dd)
}
/*
- * A secondary bus reset (SBR) issues a hot reset to our device.
- * The following routine does a 1s wait after the reset is dropped
- * per PCI Trhfa (recovery time). PCIe 3.0 section 6.6.1 -
- * Conventional Reset, paragraph 3, line 35 also says that a 1s
- * delay after a reset is required. Per spec requirements,
- * the link is either working or not after that point.
+ * This is an end around to do an SBR during probe time. A new API needs
+ * to be implemented to have cleaner interface but this fixes the
+ * current brokenness
*/
- return pci_reset_bus(dev);
+ return pci_bridge_secondary_bus_reset(dev->bus->self);
}
/*