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| author | NeilBrown <neilb@suse.de> | 2010-05-22 00:31:36 +0200 |
|---|---|---|
| committer | NeilBrown <neilb@suse.de> | 2010-05-22 00:31:36 +0200 |
| commit | 19fdb9eefb21b72edbc365b838502780c392bad6 (patch) | |
| tree | deae04c48532d6eab64ed4b0396737bb854b5506 /drivers/input/touchscreen/ad7877.c | |
| parent | md: don't insist on valid event count for spare devices. (diff) | |
| parent | sysfs: Implement sysfs tagged directory support. (diff) | |
| download | linux-19fdb9eefb21b72edbc365b838502780c392bad6.tar.xz linux-19fdb9eefb21b72edbc365b838502780c392bad6.zip | |
Merge commit '3ff195b011d7decf501a4d55aeed312731094796' into for-linus
Conflicts:
drivers/md/md.c
- Resolved conflict in md_update_sb
- Added extra 'NULL' arg to new instance of sysfs_get_dirent.
Signed-off-by: NeilBrown <neilb@suse.de>
Diffstat (limited to 'drivers/input/touchscreen/ad7877.c')
| -rw-r--r-- | drivers/input/touchscreen/ad7877.c | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/input/touchscreen/ad7877.c b/drivers/input/touchscreen/ad7877.c index eb83939c705e..0d2d7e54b465 100644 --- a/drivers/input/touchscreen/ad7877.c +++ b/drivers/input/touchscreen/ad7877.c @@ -46,7 +46,7 @@ #include <linux/spi/ad7877.h> #include <asm/irq.h> -#define TS_PEN_UP_TIMEOUT msecs_to_jiffies(50) +#define TS_PEN_UP_TIMEOUT msecs_to_jiffies(100) #define MAX_SPI_FREQ_HZ 20000000 #define MAX_12BIT ((1<<12)-1) @@ -156,9 +156,14 @@ struct ser_req { u16 reset; u16 ref_on; u16 command; - u16 sample; struct spi_message msg; struct spi_transfer xfer[6]; + + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + u16 sample ____cacheline_aligned; }; struct ad7877 { @@ -182,8 +187,6 @@ struct ad7877 { u8 averaging; u8 pen_down_acc_interval; - u16 conversion_data[AD7877_NR_SENSE]; - struct spi_transfer xfer[AD7877_NR_SENSE + 2]; struct spi_message msg; @@ -195,6 +198,12 @@ struct ad7877 { spinlock_t lock; struct timer_list timer; /* P: lock */ unsigned pending:1; /* P: lock */ + + /* + * DMA (thus cache coherency maintenance) requires the + * transfer buffers to live in their own cache lines. + */ + u16 conversion_data[AD7877_NR_SENSE] ____cacheline_aligned; }; static int gpio3; |