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| author | Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2016-08-23 20:52:40 +0200 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2016-09-05 12:41:46 +0200 |
| commit | d98de49a53e48f51332e97568127e722415e1232 (patch) | |
| tree | 8f668204ee34ba5e28f884cd52ca505eff31e62a /drivers/iommu/amd_iommu_init.c | |
| parent | iommu/amd: Implements irq_set_vcpu_affinity() hook to setup vapic mode for pa... (diff) | |
| download | linux-d98de49a53e48f51332e97568127e722415e1232.tar.xz linux-d98de49a53e48f51332e97568127e722415e1232.zip | |
iommu/amd: Enable vAPIC interrupt remapping mode by default
Introduce struct iommu_dev_data.use_vapic flag, which IOMMU driver
uses to determine if it should enable vAPIC support, by setting
the ga_mode bit in the device's interrupt remapping table entry.
Currently, it is enabled for all pass-through device if vAPIC mode
is enabled.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/amd_iommu_init.c')
| -rw-r--r-- | drivers/iommu/amd_iommu_init.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 156ab4b0f4bd..cd1713631a4a 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -146,7 +146,7 @@ struct ivmd_header { bool amd_iommu_dump; bool amd_iommu_irq_remap __read_mostly; -int amd_iommu_guest_ir; +int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static bool amd_iommu_detected; static bool __initdata amd_iommu_disabled; @@ -2019,6 +2019,11 @@ static void early_enable_iommus(void) iommu_enable(iommu); iommu_flush_all_caches(iommu); } + +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); +#endif } static void enable_iommus_v2(void) @@ -2044,6 +2049,11 @@ static void disable_iommus(void) for_each_iommu(iommu) iommu_disable(iommu); + +#ifdef CONFIG_IRQ_REMAP + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP); +#endif } /* |