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| author | Rob Clark <robdclark@chromium.org> | 2020-11-09 19:47:26 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-11-10 13:25:49 +0100 |
| commit | bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1 (patch) | |
| tree | 1d43cb88cc0f25f8f946b05ec44e4ee226f7dbab /drivers/iommu/arm/arm-smmu/arm-smmu.h | |
| parent | iommu/arm-smmu-qcom: Add implementation for the adreno GPU SMMU (diff) | |
| download | linux-bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1.tar.xz linux-bffb2eaf0ba2c0bdd7fc2c4e194dab6783f5d8c1.zip | |
iommu/arm-smmu: Add a way for implementations to influence SCTLR
For the Adreno GPU's SMMU, we want SCTLR.HUPCF set to ensure that
pending translations are not terminated on iova fault. Otherwise
a terminated CP read could hang the GPU by returning invalid
command-stream data. Add a hook to for the implementation to modify
the sctlr value if it wishes.
Co-developed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Link: https://lore.kernel.org/r/20201109184728.2463097-3-jcrouse@codeaurora.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/arm/arm-smmu/arm-smmu.h')
| -rw-r--r-- | drivers/iommu/arm/arm-smmu/arm-smmu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 9a5eb6782918..04288b6fc619 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -144,6 +144,7 @@ enum arm_smmu_cbar_type { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12) #define ARM_SMMU_SCTLR_CFCFG BIT(7) +#define ARM_SMMU_SCTLR_HUPCF BIT(8) #define ARM_SMMU_SCTLR_CFIE BIT(6) #define ARM_SMMU_SCTLR_CFRE BIT(5) #define ARM_SMMU_SCTLR_E BIT(4) @@ -437,6 +438,7 @@ struct arm_smmu_impl { struct arm_smmu_device *smmu, struct device *dev, int start); void (*write_s2cr)(struct arm_smmu_device *smmu, int idx); + void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32 reg); }; #define INVALID_SMENDX -1 |