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author | Will Deacon <will.deacon@arm.com> | 2014-02-06 15:59:05 +0100 |
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committer | Will Deacon <will.deacon@arm.com> | 2014-02-10 18:02:23 +0100 |
commit | 57ca90f6800987ac274d7ba065ae6692cdf9bcd7 (patch) | |
tree | 8b7ddc5f80bc4eb6dce0a9131b3e184899cf730b /drivers/iommu/dmar.c | |
parent | iommu/arm-smmu: fix table flushing during initial allocations (diff) | |
download | linux-57ca90f6800987ac274d7ba065ae6692cdf9bcd7.tar.xz linux-57ca90f6800987ac274d7ba065ae6692cdf9bcd7.zip |
iommu/arm-smmu: set CBARn.BPSHCFG to NSH for s1-s2-bypass contexts
Whilst trying to bring-up an SMMUv2 implementation with the table
walker plumbed into a coherent interconnect, I noticed that the memory
transactions targetting the CPU caches from the SMMU were marked as
outer-shareable instead of inner-shareable.
After a bunch of digging, it seems that we actually need to program
CBARn.BPSHCFG for s1-s2-bypass contexts to act as non-shareable in order
for the shareability configured in the corresponding TTBCR not to be
overridden with an outer-shareable attribute.
Cc: <stable@vger.kernel.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'drivers/iommu/dmar.c')
0 files changed, 0 insertions, 0 deletions