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author | Lu Baolu <baolu.lu@linux.intel.com> | 2020-01-02 01:18:16 +0100 |
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committer | Joerg Roedel <jroedel@suse.de> | 2020-01-07 14:05:58 +0100 |
commit | 87208f22a4d942ce880e7bf092158eecd6ffa293 (patch) | |
tree | 005e09f1eb211d1978cdb317c96f6b456b65d890 /drivers/iommu/intel-pasid.h | |
parent | iommu/vt-d: Add set domain DOMAIN_ATTR_NESTING attr (diff) | |
download | linux-87208f22a4d942ce880e7bf092158eecd6ffa293.tar.xz linux-87208f22a4d942ce880e7bf092158eecd6ffa293.zip |
iommu/vt-d: Add PASID_FLAG_FL5LP for first-level pasid setup
Current intel_pasid_setup_first_level() use 5-level paging for
first level translation if CPUs use 5-level paging mode too.
This makes sense for SVA usages since the page table is shared
between CPUs and IOMMUs. But it makes no sense if we only want
to use first level for IOVA translation. Add PASID_FLAG_FL5LP
bit in the flags which indicates whether the 5-level paging
mode should be used.
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu/intel-pasid.h')
-rw-r--r-- | drivers/iommu/intel-pasid.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/iommu/intel-pasid.h b/drivers/iommu/intel-pasid.h index fc8cd8f17de1..92de6df24ccb 100644 --- a/drivers/iommu/intel-pasid.h +++ b/drivers/iommu/intel-pasid.h @@ -37,6 +37,12 @@ */ #define PASID_FLAG_SUPERVISOR_MODE BIT(0) +/* + * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first- + * level translation, otherwise, 4-level paging will be used. + */ +#define PASID_FLAG_FL5LP BIT(1) + struct pasid_dir_entry { u64 val; }; |