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| author | Robin Murphy <robin.murphy@arm.com> | 2019-10-25 20:08:36 +0200 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2019-11-04 20:59:30 +0100 |
| commit | 205577ab6f7ade6185f764ed78fb6875dca40205 (patch) | |
| tree | 3dc33876b1194b7d1cf1a384e7216659a6d95344 /drivers/iommu/io-pgtable-arm.c | |
| parent | iommu/io-pgtable-arm: Simplify level indexing (diff) | |
| download | linux-205577ab6f7ade6185f764ed78fb6875dca40205.tar.xz linux-205577ab6f7ade6185f764ed78fb6875dca40205.zip | |
iommu/io-pgtable-arm: Rationalise MAIR handling
Between VMSAv8-64 and the various 32-bit formats, there is either one
64-bit MAIR or a pair of 32-bit MAIR0/MAIR1 or NMRR/PMRR registers.
As such, keeping two 64-bit values in io_pgtable_cfg has always been
overkill.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'drivers/iommu/io-pgtable-arm.c')
| -rw-r--r-- | drivers/iommu/io-pgtable-arm.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index fcb302704053..cd96442af44b 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -861,8 +861,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) (ARM_LPAE_MAIR_ATTR_INC_OWBRWA << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE)); - cfg->arm_lpae_s1_cfg.mair[0] = reg; - cfg->arm_lpae_s1_cfg.mair[1] = 0; + cfg->arm_lpae_s1_cfg.mair = reg; /* Looking good; allocate a pgd */ data->pgd = __arm_lpae_alloc_pages(ARM_LPAE_PGD_SIZE(data), |