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| author | Sohil Mehta <sohil.mehta@intel.com> | 2017-12-20 20:59:24 +0100 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2018-01-17 15:02:49 +0100 |
| commit | 5e3b4a15dd8da6bded2092694c8db3b505cbf711 (patch) | |
| tree | 34c9140038e015b08883a693734e95ced01512c9 /drivers/iommu | |
| parent | iommu/vt-d: Use domain instead of cache fetching (diff) | |
| download | linux-5e3b4a15dd8da6bded2092694c8db3b505cbf711.tar.xz linux-5e3b4a15dd8da6bded2092694c8db3b505cbf711.zip | |
iommu/vt-d: Enable upto 57 bits of domain address width
Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.
Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set the actual supported address
width to the maximum support available in IOMMU hardware.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/intel-iommu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c index 869f37d1f3b7..53227d6e911e 100644 --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c @@ -64,7 +64,7 @@ #define IOAPIC_RANGE_END (0xfeefffff) #define IOVA_START_ADDR (0x1000) -#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 +#define DEFAULT_DOMAIN_ADDRESS_WIDTH 57 #define MAX_AGAW_WIDTH 64 #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |