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| author | Adrian Huang <ahuang12@lenovo.com> | 2020-02-14 11:44:51 +0100 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2020-02-28 16:19:48 +0100 |
| commit | c20f36534666e37858a14e591114d93cc1be0d34 (patch) | |
| tree | 5d60298e8c15e3e77c00490c638f03ebe64d4793 /drivers/iommu | |
| parent | Linux 5.6-rc3 (diff) | |
| download | linux-c20f36534666e37858a14e591114d93cc1be0d34.tar.xz linux-c20f36534666e37858a14e591114d93cc1be0d34.zip | |
iommu/amd: Fix the configuration of GCR3 table root pointer
The SPA of the GCR3 table root pointer[51:31] masks 20 bits. However,
this requires 21 bits (Please see the AMD IOMMU specification).
This leads to the potential failure when the bit 51 of SPA of
the GCR3 table root pointer is 1'.
Signed-off-by: Adrian Huang <ahuang12@lenovo.com>
Fixes: 52815b75682e2 ("iommu/amd: Add support for IOMMUv2 domain mode")
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/amd_iommu_types.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index f8d01d6b00da..ca8c4522045b 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -348,7 +348,7 @@ #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) -#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) +#define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) #define DTE_GCR3_INDEX_A 0 #define DTE_GCR3_INDEX_B 1 |