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| author | Thomas Gleixner <tglx@linutronix.de> | 2021-12-11 10:51:23 +0100 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2021-12-11 10:51:23 +0100 |
| commit | b7fd35a0ad976ee8e7d4914e063410686b5fa353 (patch) | |
| tree | 340384d7d55fd94aa56ccb59bf9d33de97c92b14 /drivers/irqchip/irq-aspeed-scu-ic.c | |
| parent | Linux 5.16-rc4 (diff) | |
| parent | irqchip/irq-bcm7120-l2: Add put_device() after of_find_device_by_node() (diff) | |
| download | linux-b7fd35a0ad976ee8e7d4914e063410686b5fa353.tar.xz linux-b7fd35a0ad976ee8e7d4914e063410686b5fa353.zip | |
Merge tag 'irqchip-fixes-5.16-2' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent
Pull irqchip fixes from Marc Zyngier:
- Fix Armada-370-XP Multi-MSi allocation to be aligned on the allocation
size, as required by the PCI spec
- Fix aspeed-scu interrupt acknowledgement by directly writing to the
register instead of a read-modify-write sequence
- Use standard bitfirl helpers in the MIPS GIC driver instead of custom
constructs
- Fix the NVIC driver IPR register offset
- Correctly drop the reference of the device node in the irq-bcm7120-l2
driver
- Fix the GICv3 ITS INVALL command by issueing a following SYNC command
- Add a missing __init attribute to the init function of the Apple AIC
driver
Link: https://lore.kernel.org/r/20211210133516.664497-1-maz@kernel.org
Diffstat (limited to 'drivers/irqchip/irq-aspeed-scu-ic.c')
| -rw-r--r-- | drivers/irqchip/irq-aspeed-scu-ic.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c index f3c6855a4cef..18b77c3e6db4 100644 --- a/drivers/irqchip/irq-aspeed-scu-ic.c +++ b/drivers/irqchip/irq-aspeed-scu-ic.c @@ -76,8 +76,8 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) generic_handle_domain_irq(scu_ic->irq_domain, bit - scu_ic->irq_shift); - regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, - BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT)); + regmap_write_bits(scu_ic->scu, scu_ic->reg, mask, + BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT)); } chained_irq_exit(chip, desc); |